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CY7C09159AV_05 PDF预览

CY7C09159AV_05

更新时间: 2024-09-19 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 500K
描述
3.3V 8K/16K x 9 Synchronous Dual Port Static RAM

CY7C09159AV_05 数据手册

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CY7C09159AV  
CY7C09169AV3.3V 8K/16K  
x 9  
Synchronous Dual Port Static RAM  
CY7C09159AV  
CY7C09169AV  
3.3V 8K/16K x 9  
Synchronous Dual Port Static RAM  
• 3.3V Low operating power  
Features  
— Active = 135 mA (typical)  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
— Standby = 10 µA (typical)  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
— Shorten cycle times  
• Two Flow-Through/Pipelined devices  
— 8K x 9 organization (CY7C09159AV)  
— 16K x 9 organization (CY7C09169AV)  
• Three Modes  
— Minimize bus noise  
— Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Automatic power-down  
— Flow-Through  
— Pipelined  
— Burst  
• Commercial and industrial temperature ranges  
• Available in 100-pin TQFP  
• Pipelinedoutputmodeonbothportsallowsfast83-MHz  
operation  
• 0.35-micron CMOS for optimum speed/power  
• Pb-Free packages available  
• High-speed clock to data access 9 and 12 ns (max.)  
Logic Block Diagram  
R/WL  
OEL  
R/WR  
OER  
CE0L  
CE1L  
CE0R  
CE1R  
1
1
0
0
0/1  
0/1  
1
0
0
1
0/1  
0/1  
FT/PipeL  
FT/PipeR  
9
9
I/O0LI/O8L  
I/O0RI/O8R  
I/O  
Control  
I/O  
Control  
13/14  
13/14  
[1]  
12/13L  
[1]  
A0A  
A0A12/13R  
Counter/  
Counter/  
Address  
Register  
Decode  
CLKL  
CLKR  
ADSR  
Address  
Register  
Decode  
True Dual-Ported  
ADSL  
RAM Array  
CNTENL  
CNTRSTL  
CNTENR  
CNTRSTR  
Notes:  
1. A A for 8K; A A for 16K.  
0
12  
0
13  
Cypress Semiconductor Corporation  
Document #: 38-06053 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 6, 2005  

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