Datasheet > CY7C026A

CY7C026A

更新时间： 2024-09-18 04:10:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	362K
描述
16K x 16/18 Dual-Port Static RAM

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中文翻译

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数据手册

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CY7C026A 数据手册

25/0251

CY7C026A

CY7C036A

16K x 16/18 Dual-Port Static RAM

• Automatic power-down

Features

• Expandable data bus to 32/36 bits or more using Mas-

ter/Slave chip select when using more than one device

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flags for port-to-port communication

• Separate upper-byte and lower-byte control

• Pin select for Master or Slave

• True dual-ported memory cells which allow simulta-

neous access of the same memory location

• 16K x 16 organization (CY7C026A)

• 16K x 18 organization (CY7C036A)

• 0.35-micron CMOS for optimum speed/power

[1]

• High-speed access: 12 /15/20 ns

• Low operating power

Active: I = 180 mA (typical)

• Commercial and Industrial temperature ranges

• Available in 100-Pin TQFP

—

— Standby: I

= 0.05 mA (typical)

SB3

• Pin-compatible and functionally equivalent to IDT70261

• Fully asynchronous operation

Logic Block Diagram

R/W

8/9

[2]

I/O

–I/O

I/O

–I/O

8/9L

15/17L

15/17R

[3]

I/O –I/O

0L 7/8R

[3]

I/O

Control

I/O

Control

I/O –I/O

7/8L

Address

Decode

Address

Decode

True Dual-Ported

–A

13L

13R

RAM Array

–A

Interrupt

Semaphore

Arbitration

R/W

SEM

[4]

BUSY

INT

BUSY

INT

M/S

Notes:

1. See page 6 for Load Conditions.

2. I/O₈–I/O₁₅for x16 devices; I/O₉–I/O₁₇for x18 devices.

3. I/O₀–I/O₇for x16 devices; I/O₀–I/O₈for x18 devices.

4. BUSY is an output in master mode and an input in slave mode.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 3, 2000

12 3 4 5 6 7...17

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