Datasheet > CY7C018V

CY7C018V

更新时间： 2024-09-17 00:01:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	229K
描述
3.3V 64K/128K x 8/9 Dual-Port Static RAM

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中文翻译

获取价格

数据手册

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CY7C018V 数据手册

25/0251

CY7C008V/009V

CY7C018V/019V

3.3V 64K/128K x 8/9

Dual-Port Static RAM

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 16/18 bits or more using Mas-

ter/Slave chip select when using more than one device

Features

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 64K x 8 organization (CY7C008)

• 128K x 8 organization (CY7C009)

• 64K x 9 organization (CY7C018)

• 128K x 9 organization (CY7C019)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 15/20/25 ns

• Low operating power

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flag for port-to-port communication

• Dual Chip Enables

• Pin select for Master or Slave

• Commercial and Industrial Temperature Ranges

• Available in 100-pin TQFP

— Active: I_CC= 115 mA (typical)

— Standby: I_SB3= 10 µA (typical)

Logic Block Diagram

R/W_L

R/W_R

CE_0R

CE_0L

CE_1L

OE_L

CE_1R

CE_L

CE_R

OE_R

[1]

8/9

I/O_0L–I/O_7/8L

I/O_0R–I/O_7/8R

I/O

Control

16/17

[2]

Address

Decode

Address

Decode

True Dual-Ported

A_0L–A

_0R–A_15/16R

15/16L

RAM Array

16/17

[2]

A_0L–A

A_0R–A_15/16R

15/16L

CE_L

CE_R

Interrupt

Semaphore

Arbitration

OE_L

OE_R

R/W_L

SEM_L

R/W_R

SEM_R

[3]

BUSY_L

INT_L

BUSY_R

INT_R

M/S

Notes:

1. I/O₀–I/O₇for x8 devices; I/O₀–I/O₈for x9 devices.

2. A₀–A₁₅for 64K devices; A₀–A₁₆for 128K.

3. BUSY is an output in master mode and an input in slave mode.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06044 Rev. *B

Revised December 27, 2002

12 3 4 5 6 7...19

中文翻译

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