Datasheet > 存储 > SRAM> CY7C019V-20AXI

CY7C019V-20AXI

更新时间： 2024-09-17 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	453K
描述
3.3V 64K/128K x 8/9 Dual-Port Static RAM

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中文翻译

获取价格

数据手册

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CY7C019V-20AXI 数据手册

CY7C008/009

CY7C018/01964K/128K

x 8/9 Dual-Port Static RAM

CY7C008/009

CY7C018/019

64K/128K x 8/9 Dual-Port Static RAM

Features

• TrueDual-Portedmemorycellsthatallowsimultaneous

access of the same memory location

• Automatic power-down

• Expandable data bus to 16/18 bits or more using

Master/Slave chip select when using more than one

device

• 64K x 8 organization (CY7C008)

• 128K x 8 organization (CY7C009)

• 64K x 9 organization (CY7C018)

• 128K x 9 organization (CY7C019)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 12^[1]/15/20 ns

• Low operating power

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flags for port-to-port communication

• Dual Chip Enables

• Pin select for Master or Slave

— Active: I_CC= 180 mA (typical)

— Standby: I_SB3= 0.05 mA (typical)

• Fully asynchronous operation

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP; Pb-Free packages available

Logic Block Diagram

R/W_L

CE_0L

R/W_R

CE_0R

CE_1L

CE_1R

CE_L

CE_R

OE_L

OE_R

8/9

[2]

I/O_0L–I/O_7/8L

I/O_0R–I/O_7/8R

I/O

Control

I/O

Control

16/17

Address

Decode

Address

Decode

True Dual-Ported

[3]

A_0L–A_15/16L

A_0R–A_15/16R

RAM Array

16/17

[3]

A_0L–A_15/16L

A_0R–A_15/16R

CE_L

CE_R

OE_R

Interrupt

Semaphore

Arbitration

OE_L

R/W_L

SEM_L

R/W_R

SEM_R

[4]

BUSY_L

BUSY_R

INT_L

INT_R

M/S

Notes:

1. See page 6 for Load Conditions.

2. I/O –I/O for x8 devices; I/O –I/O for x9 devices.

3. A –A for 64K devices; A –A for 128K.

4. BUSY is an output in master mode and an input in slave mode.

Cypress Semiconductor Corporation

Document #: 38-06041 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 6, 2005

12 3 4 5 6 7...19

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