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CY7C019V-25AXC PDF预览

CY7C019V-25AXC

更新时间: 2024-11-07 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 453K
描述
3.3V 64K/128K x 8/9 Dual-Port Static RAM

CY7C019V-25AXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:LEAD FREE, PLASTIC, TQFP-100
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.79Is Samacsys:N
最长访问时间:25 nsI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:1179648 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX9
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.00005 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.165 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

CY7C019V-25AXC 数据手册

 浏览型号CY7C019V-25AXC的Datasheet PDF文件第2页浏览型号CY7C019V-25AXC的Datasheet PDF文件第3页浏览型号CY7C019V-25AXC的Datasheet PDF文件第4页浏览型号CY7C019V-25AXC的Datasheet PDF文件第5页浏览型号CY7C019V-25AXC的Datasheet PDF文件第6页浏览型号CY7C019V-25AXC的Datasheet PDF文件第7页 
CY7C008/009  
CY7C018/01964K/128K  
x 8/9 Dual-Port Static RAM  
CY7C008/009  
CY7C018/019  
64K/128K x 8/9 Dual-Port Static RAM  
Features  
• TrueDual-Portedmemorycellsthatallowsimultaneous  
access of the same memory location  
• Automatic power-down  
• Expandable data bus to 16/18 bits or more using  
Master/Slave chip select when using more than one  
device  
• 64K x 8 organization (CY7C008)  
• 128K x 8 organization (CY7C009)  
• 64K x 9 organization (CY7C018)  
• 128K x 9 organization (CY7C019)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 12[1]/15/20 ns  
• Low operating power  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flags for port-to-port communication  
• Dual Chip Enables  
• Pin select for Master or Slave  
— Active: ICC = 180 mA (typical)  
— Standby: ISB3 = 0.05 mA (typical)  
• Fully asynchronous operation  
• Commercial and Industrial temperature ranges  
• Available in 100-pin TQFP; Pb-Free packages available  
Logic Block Diagram  
R/WL  
CE0L  
R/WR  
CE0R  
CE1L  
CE1R  
CEL  
CER  
OEL  
OER  
8/9  
8/9  
[2]  
[2]  
I/O0L–I/O7/8L  
I/O0R–I/O7/8R  
I/O  
Control  
I/O  
Control  
16/17  
16/17  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
[3]  
[3]  
A0L–A15/16L  
A0R–A15/16R  
RAM Array  
16/17  
16/17  
[3]  
[3]  
A0L–A15/16L  
A0R–A15/16R  
CEL  
CER  
OER  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
SEML  
R/WR  
SEMR  
[4]  
[4]  
BUSYL  
BUSYR  
INTL  
INTR  
M/S  
Notes:  
1. See page 6 for Load Conditions.  
2. I/O –I/O for x8 devices; I/O –I/O for x9 devices.  
0
7
0
8
3. A –A for 64K devices; A –A for 128K.  
0
15  
0
16  
4. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06041 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 6, 2005  

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