Datasheet > 存储 > SRAM> CY7C0241-25AC

CY7C0241-25AC

更新时间： 2024-09-17 00:01:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		内存集成电路静态存储器
页数	文件大小	规格书
20页	771K
描述
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

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技术参数
数据手册
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CY7C0241-25AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	5.79
最长访问时间：	25 ns	其他特性：	INTERRUPT FLAG
I/O 类型：	COMMON	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0	长度：	14 mm
内存密度：	73728 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端口数量：	2
端子数量：	100	字数：	4096 words
字数代码：	4000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.015 A
最小待机电流：	2 V	子类别：	SRAMs
最大压摆率：	0.25 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

CY7C0241-25AC 数据手册

CY7C024/0241

CY7C025/0251

4K x 16/18 and 8K x 16/18 Dual-Port

Static RAM with SEM, INT, BUSY

Features

Functional Description

• True Dual-Ported memory cells which allow

The CY7C024/0241 and CY7C025/0251 are low-power

simultaneous reads of the same memory location

• 4K x 16 organization (CY7C024)

• 4K x 18 organization (CY7C0241)

• 8K x 16 organization (CY7C025)

• 8K x 18 organization (CY7C0251)

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Var-

ious arbitration schemes are included on the CY7C024/0241

and CY7C025/0251 to handle situations when multiple pro-

cessors access the same piece of data. Two ports are provid-

ed, permitting independent, asynchronous access for reads

and writes to any location in memory. The CY7C024/0241 and

CY7C025/0251 can be utilized as standalone 16-/18-bit du-

al-port static RAMs or multiple devices can be combined in

order to function as a 32-/36-bit or wider master/slave du-

al-port static RAM. An M/S pin is provided for implementing

32-/36-bit or wider memory applications without the need for

separate master and slave devices or additional discrete logic.

Application areas include interprocessor/multiprocessor de-

signs, communications status buffering, and dual-port vid-

eo/graphics memory.

• Low operating power: I_CC= 150 mA (typ.)

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 32/36 bits or more using

Master/Slave chip select when using more than one

device

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

Each port has independent control pins: Chip Enable (CE),

Read or Write Enable (R/W), and Output Enable (OE). Two flags

are provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being accessed by

the other port. The Interrupt Flag (INT) permits communication be-

tween ports or systems by means of a mail box. The semaphores are

used to pass a flag, or token, from one port to the other to indicate that

a shared resource is in use. The semaphore logic is comprised of

eight shared latches. Only one sidecan control the latch (semaphore)

at any time. Control of a semaphore indicates that a shared resource

is in use. An automatic power-down feature is controlled indepen-

dently on each port by a chip select (CE) pin.

• INT flag for port-to-port communication

• Separate upper-byte and lower-byte control

• Pin select for Master or Slave

• Available in 84-pin PLCC and 100-pin TQFP

The CY7C024/0241 and CY7C025/0251 are available in

84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin

Thin Quad Plastic Flatpack (TQFP).

Logic Block Diagram

R/W

[3]

15L

[3]

[2]

–

I/O –I/O

I/O

15R

I/O

CONTROL

I/O

CONTROL

[2]

I/O –I/O

I/O

[1]

BUSY

(CY7C025/0251)

12R

(CY7C025/0251)

12L

MEMORY

ARRAY

11L

ADDRESS

DECODER

ADDRESS

DECODER

11R

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

7C024–1

INT

M/S

INT

Cypress Semiconductor Corporation

Document #: 38-06035 Rev. *B

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised June 22, 2004

12 3 4 5 6 7...20

中文翻译

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CY7C0241-25AC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C09349AV-9AXC	CYPRESS	功能相似	3.3 V 4 K/8 K Ã 18 Synchronous Dual Port Sta

与CY7C0241-25AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C0241-25AI	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-25AXC	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-25AXI	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-35AC	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-35ACT	CYPRESS	获取价格	Dual-Port SRAM, 4KX18, 35ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C0241-35AI	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-35AXC	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-35AXI	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-55AC	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C0241-55AI	CYPRESS	获取价格	4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

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