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CY7C0241AV-20ACT PDF预览

CY7C0241AV-20ACT

更新时间: 2024-09-17 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 248K
描述
Dual-Port SRAM, 4KX18, 20ns, CMOS, PQFP100, PLASTIC, TQFP-100

CY7C0241AV-20ACT 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.78
Is Samacsys:N最长访问时间:20 ns
JESD-30 代码:S-PQFP-G100长度:14 mm
内存密度:73728 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18功能数量:1
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX18封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

CY7C0241AV-20ACT 数据手册

 浏览型号CY7C0241AV-20ACT的Datasheet PDF文件第2页浏览型号CY7C0241AV-20ACT的Datasheet PDF文件第3页浏览型号CY7C0241AV-20ACT的Datasheet PDF文件第4页浏览型号CY7C0241AV-20ACT的Datasheet PDF文件第5页浏览型号CY7C0241AV-20ACT的Datasheet PDF文件第6页浏览型号CY7C0241AV-20ACT的Datasheet PDF文件第7页 
CY7C024AV/025AV/026AV  
CY7C0241AV/0251AV/036AV  
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM  
• Automatic power-down  
Features  
• Expandable data bus to 32/36 bits or more using  
Master/Slave chip select when using more than one  
device  
• True dual-ported memory cells which allow  
simultaneous access of the same memory location  
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)  
• 4/8K × 18 organization (CY7C0241AV/0251AV)  
• 16K × 18 organization (CY7C036AV)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 20 and 25 ns  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Pin select for Master or Slave  
• Low operating power  
• Commercial and industrial temperature ranges  
• Available in 100-pin Lead (Pb)-free TQFP and 100-pin  
TQFP  
— Active: ICC = 115 mA (typical)  
Standby: ISB3 = 10 μA (typical)  
• Fully asynchronous operation  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CEL  
CER  
LBL  
LBR  
OEL  
OER  
[1]  
8/9  
[1]  
8/9  
I/O8/9L–I/O15/17L  
I/O8/9L–I/O15/17R  
[2]  
8/9  
8/9  
I/O  
Control  
I/O  
Control  
[2]  
I/O0L–I/O7/8L  
I/O0L–I/O7/8R  
12/13/14  
12/13/14  
[3]  
[3]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A0L–A11/1213L  
A0R–A11/12/13R  
RAM Array  
[3]  
[3]  
12/13/14  
12/13/14  
A0L–A11/12/13L  
A0R–A11/12/13R  
CER  
CEL  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
OER  
R/WR  
SEML  
[4]  
SEMR  
[4]  
BUSYL  
INTL  
UBL  
BUSYR  
INTR  
UBR  
LBL  
M/S  
LBR  
Notes:  
1. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
0
7
0
8
3. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.  
0
11  
0
12  
0
13  
4. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06052 Rev. *H  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised June 15, 2005  

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