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CY7C024-15JXCT PDF预览

CY7C024-15JXCT

更新时间： 2024-11-09 13:00:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
21页 518K
描述
Dual-Port SRAM, 4KX16, 15ns, CMOS, PQCC84, LEAD FREE, PLASTIC, LCC-84

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中文翻译

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CY7C024-15JXCT 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：84
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.6
最长访问时间：15 nsJESD-30 代码：S-PQCC-J84
JESD-609代码：e3长度：29.3116 mm
内存密度：65536 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：16功能数量：1
端子数量：84字数：4096 words
字数代码：4000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4KX16封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：29.3116 mmBase Number Matches：1

CY7C024-15JXCT 数据手册

 浏览型号CY7C024-15JXCT的Datasheet PDF文件第2页浏览型号CY7C024-15JXCT的Datasheet PDF文件第3页浏览型号CY7C024-15JXCT的Datasheet PDF文件第4页浏览型号CY7C024-15JXCT的Datasheet PDF文件第5页浏览型号CY7C024-15JXCT的Datasheet PDF文件第6页浏览型号CY7C024-15JXCT的Datasheet PDF文件第7页 
CY7C024/024A/0241  
CY7C025/0251  
4K x 16/18 and 8K x 16/18 Dual-Port  
Static RAM with SEM, INT, BUSY  
Features  
Functional Description  
■
True dual-ported memory cells, which allow simultaneous  
The CY7C024/024A/0241 and CY7C025/0251 are low power  
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various  
arbitration schemes are included on the CY7C024/ 0241 and  
CY7C025/0251 to handle situations when multiple processors  
access the same piece of data. Two ports are provided,  
permitting independent, asynchronous access for reads and  
writes to any location in memory. The CY7C024/ 0241 and  
CY7C025/0251 can be used as standalone 16 or 18-bit dual-port  
static RAMs or multiple devices can be combined to function as  
a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S  
pin is provided for implementing 32-/36-bit or wider memory  
applications without the need for separate master and slave  
devices or additional discrete logic. Application areas include  
interprocessor/multiprocessor designs, communications status  
buffering, and dual-port video/graphics memory.  
reads of the same memory location  
4K x 16 organization (CY7C024/024A[1]  
4K x 18 organization (CY7C0241)  
8K x 16 organization (CY7C025)  
8K x 18 organization (CY7C0251)  
■
■
■
■
■
■
■
■
■
■
)
0.65 micron CMOS for optimum speed and power  
High speed access: 15 ns  
Low operating power: ICC = 150 mA (typ)  
Fully asynchronous operation  
Automatic power down  
Each port has independent control pins: Chip Enable (CE), Read  
or Write Enable (R/W), and Output Enable (OE). Two flags are  
provided on each port (BUSY and INT). BUSY signals that the  
port is trying to access the same location currently being  
accessed by the other port. The Interrupt Flag (INT) permits  
communication between ports or systems by means of a mail  
box. The semaphores are used to pass a flag, or token, from one  
port to the other to indicate that a shared resource is in use. The  
semaphore logic is comprised of eight shared latches. Only one  
side can control the latch (semaphore) at any time. Control of a  
semaphore indicates that a shared resource is in use. An  
automatic power down feature is controlled independently on  
each port by a chip select (CE) pin.  
Expandable data bus to 32/36 bits or more using Master/Slave  
chip select when using more than one device  
■
■
On-chip arbitration logic  
Semaphores included to permit software handshaking  
between ports  
■
■
■
■
INT flag for port-to-port communication  
Separate upper-byte and lower-byte control  
Pin select for Master or Slave  
Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin  
(Pb-free) TQFP, and 100-pin TQFP  
The CY7C024/024A/0241 and CY7C025/0251 are available in  
84-pin Pb-free PLCCs, 84-pin PLCCs (CY7C024 and CY7C025  
only), 100-pin Pb-free Thin Quad Plastic Flatplack (TQFP), and  
100-pin Thin Quad Plastic Flatpack.  
Note  
1. CY7C024 and CY7C024A are functionally identical.  
Cypress Semiconductor Corporation  
Document #: 38-06035 Rev. *D  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised December 09, 2008  
[+] Feedback  
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