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CY7C017A-15JI PDF预览

CY7C017A-15JI

更新时间: 2024-09-16 23:45:15
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器
页数 文件大小 规格书
20页 499K
描述
x9 Dual-Port SRAM

CY7C017A-15JI 数据手册

 浏览型号CY7C017A-15JI的Datasheet PDF文件第2页浏览型号CY7C017A-15JI的Datasheet PDF文件第3页浏览型号CY7C017A-15JI的Datasheet PDF文件第4页浏览型号CY7C017A-15JI的Datasheet PDF文件第5页浏览型号CY7C017A-15JI的Datasheet PDF文件第6页浏览型号CY7C017A-15JI的Datasheet PDF文件第7页 
CY7C007A  
CY7C017A32K/16K x 8, 32K x 9  
Dual-Port Static RAM  
1
CY7C006A, CY7C007A  
CY7C016A, CY7C017A  
32K/16K x8, 32K/16K x9  
Dual-Port Static RAM  
• Automatic power-down  
Features  
• Expandable data bus to 16/18 bits or more using Mas-  
ter/Slave chip select when using more than one device  
• On-chip arbitration logic  
• True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
• 16K x 8 organization (CY7C006A)  
• 32K x 8 organization (CY7C007A)  
• 16K x 9 organization (CY7C016A)  
• 32K x 9 organization (CY7C017A)  
• 0.35-micron CMOS for optimum speed/power  
• Semaphores included to permit software handshaking  
between ports  
• INT flags for port-to-port communication  
• Pin select for Master or Slave  
• Commercial temperature range  
[1]  
• High-speed access: 12 /15/20 ns  
• Low operating power  
• Available in 68-pin PLCC (CY7C006A, CY7C007A and  
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin  
TQFP (CY7C007A and CY7C016A)  
• Pin-compatible and functionally equivalent to IDT7006  
and IDT7007  
— Active: I = 180 mA (typical)  
CC  
— Standby: I  
= 0.05 mA (typical)  
SB3  
• Fully asynchronous operation  
Logic Block Diagram  
R/W  
R/W  
CE  
L
R
R
R
CE  
L
OE  
OE  
L
[2]  
[2]  
8/9  
8/9  
I/O –I/O  
I/O –I/O  
0R 7/8R  
0L  
7/8L  
I/O  
I/O  
Control  
Control  
14/15  
14/15  
[4]  
13/14R  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
[4]  
A
A
–A  
A
A
–A  
–A  
0L  
0L  
13/14L  
0R  
RAM Array  
14/15  
14/15  
[4]  
13/14R  
[4]  
13/14L  
–A  
0R  
CE  
CE  
Interrupt  
Semaphore  
Arbitration  
L
R
OE  
OE  
L
R
R/W  
SEM  
R/W  
SEM  
L
R
R
L
[3]  
L
[3]  
BUSY  
INT  
BUSY  
INT  
R
R
L
M/S  
Notes:  
1. See page 7 for Load Conditions.  
2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.  
3. BUSY is an output in master mode and an input in slave mode.  
4. A0–A13 for 16K; A0–A14 for 32K devices.  
For the most recent information, visit the Cypress web site at www.cypress.com  
ypress Semiconductor Corporation  
C
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
January 10, 2001  

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