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CY2CC1810OCT PDF预览

CY2CC1810OCT

更新时间: 2024-11-20 22:07:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 逻辑集成电路光电二极管驱动时钟
页数 文件大小 规格书
8页 131K
描述
1:10 Clock Fanout Buffer with Output Enable

CY2CC1810OCT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP24,.3
针数:24Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.8系列:2CC
输入调节:SCHMITT TRIGGERJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:8.2 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:10最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP24,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5/3.3 VProp。Delay @ Nom-Sup:3.9 ns
传播延迟(tpd):3.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.99 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.29 mmBase Number Matches:1

CY2CC1810OCT 数据手册

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COMLINK™ SERIES  
CY2CC1810  
1:10 Clock Fanout Buffer with Output Enable  
Features  
Description  
Low-voltage operation  
VDD range from 2.5 to 3.3V  
1:10 fanout  
The Cypress series of network circuits is produced using  
advanced 0.35-micron CMOS technology, achieving the  
industries fastest logic and buffers.  
The Cypress CY2CC1810 fanout buffer features one input and  
ten three-state outputs.  
Drives either a 50-ohm or 75-ohm transmission line  
Over voltage tolerant input hot swappable  
Low input capacitance  
Low output skew  
Low propagation delay  
Designed for data communications clock management appli-  
cations, the large fanout from a single input reduces loading  
on the input clock.  
AVCMOS-type outputs dynamically adjust for variable  
impedance-matching and eliminate the need for series-  
damping resistors; they also reduce noise overall.  
Typical (tpd < 4 ns)  
High-speed operation > 200 MHz  
LVTTL-/LVCMOS-compatible input  
Output disable to three-state  
Industrial versions available  
Packages available include: SOIC/SSOP  
Block Diagram  
Pin Configuration  
Q1  
OE#  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
GND  
Q10  
VDD  
Q9  
GND  
Q1  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VDD  
Q2  
VDD  
OE#  
IN  
GND  
GND  
Q3  
Q4  
GND  
Q8  
GND  
Q5  
VDD  
Q6  
9
IN  
VDD  
Q7  
10  
11  
12  
GND  
GND  
24 pin SOIC/SSOP  
GND  
OUTPUT (AVCMOS)  
Pin Description  
Pin Number  
Pin Name  
GND  
Pin Description  
Power  
1,7,8,12,13,17,20,24  
Ground  
3,10,15,22  
VDD  
Power Supply  
Output Enable  
Input  
Power  
5
OE#  
LVTTL/LVCMOS  
6
IN  
LVTTL/LVCMOS  
AVCMOS  
2,4,9,11,14,16,18,19,21,23  
Q10........Q1  
Output  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07055 Rev. *C  
Revised December 14, 2002  

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