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CY29350AXIT PDF预览

CY29350AXIT

更新时间: 2024-01-07 13:56:21
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟驱动器时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
13页 431K
描述
2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock lines

CY29350AXIT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:7 X 7 MM, 1 MM HEIGHT, LEAD FREE, TQFP-32
针数:32Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.75Is Samacsys:N
其他特性:OPERATES AT 2.5 V MINIMUM SUPPLY AT 190MHZ, 95 MHZ, 47.5 MHZJESD-30 代码:S-PQFP-G32
长度:7 mm端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE主时钟/晶体标称频率:31.25 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY29350AXIT 数据手册

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CY29350  
2.5 V or 3.3 V, 200-MHz,  
9-Output Clock Driver  
2.5  
V or 3.3 V, 200-MHz, 9-Output Clock Driver  
Features  
Functional Description  
Output frequency range: 25 MHz to 200 MHz  
Input frequency range: 6.25 MHz to 31.25 MHz  
2.5 V or 3.3 V operation  
The CY29350 is a low-voltage high-performance 200-MHz  
PLL-based clock driver designed for high speed clock  
distribution applications.  
The CY29350 features Xtal and LVCMOS reference clock inputs  
and provides nine outputs partitioned in four banks of 1, 1, 2, and  
5 outputs. Bank A divides the VCO output by 2 or 4 while the  
other banks divide by 4 or 8 per SEL(A:D) settings, see . These  
dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1.  
Each LVCMOS compatible output can drive 50 series or  
parallel terminated transmission lines. For series terminated  
transmission lines, each output can drive one or two traces giving  
the device an effective fanout of 1:18.  
Split 2.5 V/3.3 V outputs  
±2.5% max Output duty cycle variation  
Nine Clock outputs: Drive up to 18 clock lines  
Two reference clock inputs: Xtal or LVCMOS  
150-ps max output-output skew  
Phase-locked loop (PLL) bypass mode  
Spread Aware™  
The PLL is ensured stable given that the VCO is configured to  
run between 200 MHz to 500 MHz. This allows a wide range of  
output frequencies from 25 MHz to 200 MHz. The internal VCO  
is running at multiples of the input reference clock set by the  
feedback divider, see Table 1.  
Output enable/disable  
Pin-compatible with MPC9350  
When PLL_EN is LOW, PLL is bypassed and the reference clock  
directly feeds the output dividers. This mode is fully static and the  
minimum input clock frequency specification does not apply.  
Industrial temperature range: –40 °C to +85 °C  
32-pin 1.0 mm TQFP package  
Block Diagram  
SELA  
PLL_EN  
REF_SEL  
TCLK  
VCO  
200 -  
500MHz  
Phase  
Detector  
QA  
QB  
  
  
XIN  
OSC  
XOUT  
LPF  
  
FB_SEL  
SELB  
QC0  
QC1  
  
  
SELC  
QD0  
QD1  
SELD  
OE#  
QD2  
QD3  
QD4  
Cypress Semiconductor Corporation  
Document Number: 38-07474 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 12, 2011  
[+] Feedback  

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