Datasheet > CY29351_08

CY29351_08

更新时间： 2024-09-24 04:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	318K
描述
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay

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数据手册

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CY29351_08 数据手册

PRELIMINARY

CY29351

2.5V or 3.3V, 200 MHz,

9-Output Zero Delay

Features

Functional Description

■ Output frequency range: 25 MHz to 200 MHz

■ Input frequency range: 25 MHz to 200 MHz

■ 2.5V or 3.3V operation

The CY29351 is a low voltage high performance 200 MHz

PLL-based zero delay buffer designed for high speed clock distri-

bution applications.

The CY29351 features LVPECL and LVCMOS reference clock

inputs and provides 9 outputs partitioned in four banks of one,

one, two, and five outputs. Bank A divides the VCO output by two

or four while the other banks divide by four or eight per SEL(A:D)

settings (Table 3, “Function Table,” on page 3). These dividers

allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each

LVCMOS compatible output can drive 50Ω series or parallel

terminated transmission lines. For series terminated trans-

mission lines, each output can drive one or two traces giving the

device an effective fanout of 1:18.

■ Split 2.5V/3.3V outputs

■ ±2.5% max Output duty cycle variation

■ 9 clock outputs: Drive up to 18 clock lines

■ Two reference clock inputs: LVPECL or LVCMOS

■ 150-ps max output-output skew

■ Phase-locked loop (PLL) bypass mode

■ Spread Aware™

The PLL is ensured stable given that the VCO is configured to

run between 200 MHz to 500 MHz. This allows a wide range of

output frequencies from 25 MHz to 200 MHz. For normal

operation, the external feedback input, FB_IN, is connected to

one of the outputs. The internal VCO is running at multiples of

the input reference clock set by the feedback divider (Table 2,

“Frequency Table,” on page 3).

■ Output enable/disable

■ Pin-compatible with MPC9351

■ Industrial temperature range: –40°C to +85°C

■ 32-pin 1.0-mm TQFP package

When PLL_EN# is LOW, PLL is bypassed and the reference

clock directly feeds the output dividers. This mode is fully static

and the minimum input clock frequency specification does not

apply.

Block Diagram

SELA

PLL_EN

REF_SEL

TCLK

VCO

200 -

500 MHz

Phase

Detector

÷2 / ÷4

÷4 / ÷8

PECL_CLK

LPF

FB_IN

SELB

QC0

QC1

÷4 / ÷8

SELC

OE#

QD0

QD1

SELD

QD2

QD3

QD4

Cypress Semiconductor Corporation

Document Number: 38-07475 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 21, 2008

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与CY29351_08相关器件

型号	品牌	获取价格	描述	数据表
CY29351_09	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
CY29351AI	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
CY29351AIT	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
CY29351AXI	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 9-Output Zero Delay
CY29351AXIT	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 9-Output Zero Delay
CY29352	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29352_07	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29352_08	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
CY29352_11	CYPRESS	获取价格	2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer
CY29352_12	CYPRESS	获取价格	2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer

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