CY29351

更新时间： 2024-09-23 22:10:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
8页	288K
描述
2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer

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CY29351 数据手册

CY29351

2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer

Features

Functional Description

• Output frequency range: 25 MHz to 200 MHz

• Input frequency range: 25 MHz to 200 MHz

• 2.5V or 3.3V operation

The CY29351 is a low voltage high performance 200 MHz

PLL-based zero delay buffer designed for high speed clock

distribution applications.

The CY29351 features LVPECL and LVCMOS reference clock

inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2,

and 5 outputs. Bank A divides the VCO output by 2 or 4 while

the other banks divide by 4 or 8 per SEL(A:D) settings, see

Functional Table. These dividers allow output to input ratios of

4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output

can drive 50Ω series or parallel terminated transmission lines.

For series terminated transmission lines, each output can

drive one or two traces giving the device an effective fanout of

1:18.

The PLL is ensured stable given that the VCO is configured to

run between 200 MHz to 500 MHz. This allows a wide range

of output frequencies from 25 MHz to 200 MHz. For normal

operation, the external feedback input, FB_IN, is connected to

one of the outputs. The internal VCO is running at multiples of

the input reference clock set by the feedback divider, see the

Table 1.

• Split 2.5V/3.3V outputs

• ±2.5% max Output duty cycle variation

• 9 Clock outputs: Drive up to 18 clock lines

• Two reference clock inputs: LVPECL or LVCMOS

• 150-ps max output-output skew

• Phase-locked loop (PLL) bypass mode

• Spread Aware™

• Output enable/disable

• Pin-compatible with MPC9351

• Industrial temperature range: –40°C to +85°C

• 32-Pin 1.0-mm TQFP package

When PLL_EN is LOW, PLL is bypassed and the reference

clock directly feeds the output dividers. This mode is fully static

and the minimum input clock frequency specification does not

apply.

Pin Configuration

Block Diagram

SELA

PLL_EN

REF_SEL

TCLK

VCO

Phase

÷2 / ÷4

AVDD

FB_IN

QC0

VDDQC

QC1

VSS

QD0

VDDQD

QD1

VSS

PECL_CLK

200 -

Detector

500 MHz

SELA

SELB

÷4 / ÷8

CY29351

SELC

LPF

SELD

AVSS

PECL_CLK

FB_IN

SELB

QC0

QC1

SELC

OE#

QD0

QD1

÷4 / ÷8

SELD

QD2

QD3

QD4

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07475 Rev. *A

Revised July 26, 2004

12 3 4 5 6 7 8

中文翻译

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与CY29351相关器件

型号	品牌	获取价格	描述	数据表
CY29351_08	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 9-Output Zero Delay
CY29351_09	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
CY29351AI	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
CY29351AIT	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
CY29351AXI	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 9-Output Zero Delay
CY29351AXIT	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 9-Output Zero Delay
CY29352	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29352_07	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29352_08	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
CY29352_11	CYPRESS	获取价格	2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer

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