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CY29430FLQXIT PDF预览

CY29430FLQXIT

更新时间: 2024-11-06 01:11:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
24页 1957K
描述
Low-noise PLL for high-performance clock applications

CY29430FLQXIT 数据手册

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CY29430  
High-Performance Clock Synthesizer  
High-Performance Clock Synthesizer  
Features  
Functional Description  
Low-noise PLL for high-performance clock applications  
The CY29430 is a Programmable PLL based crystal oscillator  
solution with flexible output frequency options. It is field and  
factory programmable for any output frequency between 15 MHz  
and 2.1 GHz. Four frequencies are independently programmable  
on the differential output with the frequency select (FS) pins.  
Additionally, other frequency options can be configured with the  
I2C interface. Using advanced design technology, it provides  
excellent jitter performance across the entire output frequency  
range working reliably at supply voltages from 1.8 V to 3.3 V for  
ambient temperatures from –40 °C to +105 °C. This makes it  
ideally suited for communications applications (for example,  
OTN, SONET/SDH, xDSL, GbE, Networking, Wireless  
Infrastructure), test and instrumentation applications, and high  
speed data converters. Additionally, the VCXO function enables  
the use of CY29430 in applications requiring a clock source with  
voltage control and in discrete clocking solutions for  
synchronous timing applications.  
Differential Clock Output: Four frequencies selectable,  
reconfigurable by I2C  
Output frequency support from 15 MHz to 2.1 GHz  
Fractional N PLL with fully integrated VCO  
Works on third overtone (OT3) of a fixed frequency crystal, Low  
frequency fundamental (LFF), High frequency fundamental  
(HFF) mode crystal and Low Frequency Input  
LVPECL, CML, HCSL, LVDS or LVCMOS output standards  
available  
Compatible with 3.3 V, 2.5 V, and 1.8 V supply  
150 fs typical integrated jitter performance (12 kHz to 20 MHz  
frequency offsets) for output greater than 150 MHz  
The CY29430 device configuration can be created using  
ClockWizard 2.1. For programming support, contact Cypress  
technical support or send an email to clocks@cypress.com.  
VCXO functionality provided with tunable Total Pull Range  
(TPR) from +/- 50 ppm to +/- 275 ppm  
16 pin QFN package: 3 × 3 × 0.6 mm  
For a complete list of related documentation, click here.  
Logic Block Diagram  
VDD  
GND  
VDDO  
CLK_P  
XOUT  
Crystal  
Oscillator  
Output  
CLK_N  
Fractional - N  
Output  
Dividers  
Drivers  
LC VCO Based PLL  
CLK_SE  
XIN  
Digital Configuration and Control  
ADC + Digital Filtering Pathway  
(for VCXO Function)  
I2C  
Interface  
NVM  
SCL  
SDA  
VC  
OE  
FS[1:0]  
Cypress Semiconductor Corporation  
Document Number: 002-11000 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 3, 2017  

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