Datasheet > CY29352_07

CY29352_07

更新时间： 2024-09-24 04:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	246K
描述
2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer

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CY29352_07 数据手册

CY29352

2.5V or 3.3V, 200-MHz, 11-Output

Zero Delay Buffer

Features

Description

• Output frequency range: 16.67 MHz to 200 MHz

• Input frequency range: 16.67 MHz to 200 MHz

• 2.5V or 3.3V operation

The CY29352 is a low-voltage high-performance 200 MHz

PLL-based zero delay buffer designed for high-speed clock

distribution applications.

The CY29352 features an LVCMOS reference clock input and

provides 11 outputs partitioned in 3 banks of 5, 4, and 2

outputs. Bank A divides the VCO output by 4 or 6 while Bank

B divides by 4 and 2 and Bank C divides by 2 and 4 per

SEL(A:C) settings, see Table 2, “Function Table,” on page 2.

These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1,

2:3, 1:2, and 1:3. Each LVCMOS compatible output drives 50Ω

series or parallel terminated transmission lines. For series

terminated transmission lines, each output drives one or two

traces giving the device an effective fanout of 1:22.

• Split 2.5V/3.3V outputs

• ±2% max Output duty cycle variation

• 11 Clock outputs: Drive up to 22 clock lines

• LVCMOS reference clock input

• 125-ps max output-output skew

• PLL bypass mode

• Spread Aware™

• Output enable/disable

The PLL is ensured stable if the VCO is configured to run

between 200 MHz to 500 MHz. This allows a wide range of

output frequencies from 16.67 MHz to 200 MHz. For normal

operation, the external feedback input, FB_IN, is connected to

one of the outputs. The internal VCO is running at multiples of

the input reference clock set by the feedback divider, see

Table 1, “Frequency Table,” on page 2.

• Pin compatible with MPC9352 and MPC952

• Industrial temperature range: –40°C to +85°C

• 32-pin 1.0-mm TQFP package

When PLL_EN# is HIGH, PLL is bypassed and the reference

clock directly feeds the output dividers. This mode is fully static

and the minimum input clock frequency specification does not

apply.

Block Diagram

PLL_EN#

Pin Configuration

REFCLK

QA0

Phase

Detector

VCO

200-500MHz

÷4 /

÷6

÷2

QA1

QA2

QA3

QA4

FB_IN

LPF

VCO_SEL

SELC

VSS

VCO_SEL

SELA

QB1

QB0

VDDQB

VDDQA

QA4

SELB

SELA

MR/OE#

REFCLK

AVSS

CY29352

÷4 /

÷2

QB0

QB1

QA3

VSS

FB_IN

SELB

QB2

QB3

QC0

QC1

÷2 /

÷4

SELC

MR/OE#

Cypress Semiconductor Corporation

Document #: 38-07476 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 26, 2007

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与CY29352_07相关器件

型号	品牌	获取价格	描述	数据表
CY29352_08	CYPRESS	获取价格	2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
CY29352_11	CYPRESS	获取价格	2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer
CY29352_12	CYPRESS	获取价格	2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer
CY29352AI	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29352AIT	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29352AXI	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29352AXIT	CYPRESS	获取价格	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
CY29422FLXIT	CYPRESS	获取价格	Processor Specific Clock Generator, 2100MHz, CMOS, CQCC8, LCC-8
CY29430	CYPRESS	获取价格	Low-noise PLL for high-performance clock applications
CY29430FLQXI	INFINEON	获取价格	Programmable High-Frequency Crystal Oscillator

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