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CY2318ANZOXC-11 PDF预览

CY2318ANZOXC-11

更新时间: 2024-09-05 22:05:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 动态存储器PC
页数 文件大小 规格书
9页 185K
描述
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs

CY2318ANZOXC-11 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.71系列:2318
输入调节:STANDARDJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:48实输出次数:18
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:2.794 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:7.5 mmBase Number Matches:1

CY2318ANZOXC-11 数据手册

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CY2318ANZ  
18 Output, 3.3V SDRAM Buffer for  
Desktop PCs with 4 DIMMs  
Functional Description  
Features  
• One input to 18 output buffer/driver  
• Supports up to four SDRAM DIMMs  
• Two additional outputs for feedback  
• Serial interface for individual output control  
• 150ps typical output-output skew  
• Up to 100 MHz operation  
• Dedicated OE pin for testing  
• Space-saving 48-pin SSOP package  
• 3.3V operation  
The CY2318ANZ is a 3.3V buffer designed to distribute  
high-speed clocks in PC applications. The part has 18 outputs,  
16 of which can be used to drive up to four SDRAM DIMMs,  
and the remaining can be used for external feedback to a PLL.  
The device operates at 3.3V and outputs can run up to 100  
MHz, thus making it compatible with Pentium II® processors.  
The CY2318ANZ can be used in conjunction with the CY2280,  
CY2281, CY2282 or similar clock synthesizer for a complete  
Pentium II motherboard solution.  
The CY2318ANZ also includes a serial interface which can  
enable or disable each output clock. On power-up, all output  
clocks are enabled (internal pull up). A separate Output  
Enable pin facilitates testing on ATE.  
Block Diagram  
Pin Configuration  
SSOP  
Top View  
1
NC  
NC  
48  
47  
NC  
BUF_IN  
2
NC  
SDRAM0  
SDRAM1  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD  
VDD  
SDRAM0  
SDRAM1  
VSS  
SDRAM15  
SDRAM14  
VSS  
SDRAM2  
SDRAM3  
VDD  
VDD  
SDRAM4  
SDRAM5  
SDRAM6  
SDRAM7  
SDRAM8  
SDRAM2  
SDRAM13  
SDRAM12  
VSS  
SDRAM3  
VSS  
SDATA  
BUF_IN  
VDD  
OE  
Serial Interface  
Decoding  
VDD  
SDRAM9  
SDRAM4  
SDRAM5  
SDRAM11  
SDRAM10  
VSS  
SCLOCK  
SDRAM10  
VSS  
VDD  
SDRAM11  
VDD  
SDRAM12  
SDRAM13  
SDRAM14  
SDRAM15  
SDRAM16  
SDRAM17  
SDRAM6  
SDRAM7  
VSS  
SDRAM9  
SDRAM8  
VSS  
VDD  
VDD  
SDRAM16  
VSS  
SDRAM17  
VSS  
VDDIIC  
VSSIIC  
SCLOCK  
OE  
SDATA  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07181 Rev. *B  
Revised January 19, 2005  

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