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CY2318BNZPVC-11T PDF预览

CY2318BNZPVC-11T

更新时间: 2024-11-27 19:55:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 94K
描述
Low Skew Clock Driver, 2318 Series, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48

CY2318BNZPVC-11T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.77系列:2318
输入调节:STANDARDJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:15.875 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:48实输出次数:18
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:2.794 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mm最小 fmax:133 MHz
Base Number Matches:1

CY2318BNZPVC-11T 数据手册

 浏览型号CY2318BNZPVC-11T的Datasheet PDF文件第2页浏览型号CY2318BNZPVC-11T的Datasheet PDF文件第3页浏览型号CY2318BNZPVC-11T的Datasheet PDF文件第4页浏览型号CY2318BNZPVC-11T的Datasheet PDF文件第5页浏览型号CY2318BNZPVC-11T的Datasheet PDF文件第6页浏览型号CY2318BNZPVC-11T的Datasheet PDF文件第7页 
CY2318BNZ  
18 Output, 3.3V SDRAM Buffer for  
Desktop PCs with 4 DIMMs  
Functional Description  
Features  
• One input to 18 output buffer/driver  
• Supports up to four SDRAM DIMMs  
• Two additional outputs for feedback  
• SMBus interface for individual output control  
• Low skew outputs (< 200 ps)  
The CY2318BNZ is a 3.3V buffer designed to distribute  
high-speed clocks in PC applications. The part has 18 outputs,  
16 of which can be used to drive up to four SDRAM DIMMs,  
and the remaining can be used for external feedback to a PLL.  
The device operates at 3.3V and outputs can run up to 100  
MHz, thus making it compatible with Pentium II® processors.  
The CY2318BNZ can be used in conjunction with the CY2280,  
CY2281, CY2282 or similar clock synthesizer for a complete  
Pentium II motherboard solution.  
• Up to 100 MHz operation for Industrial temperatures  
• Up to 133 MHz operation for Commercial temperatures  
• Dedicated OE pin for testing  
The CY2318BNZ also includes an SMBus interface which can  
enable or disable each output clock. On power-up, all output  
clocks are enabled (internal pull up). A separate Output Enable  
pin facilitates testing on ATE.  
• Space-saving 48-pin SSOP package  
• 3.3V operation  
Block Diagram  
Pin Configuration  
SSOP  
Top View  
1
NC  
NC  
48  
47  
NC  
NC  
V
SDRAM15  
SDRAM14  
BUF_IN  
2
SDRAM0  
SDRAM1  
3
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
V
DD  
DD  
4
SDRAM0  
SDRAM1  
5
SDRAM2  
SDRAM3  
6
V
V
SS  
SS  
7
V
V
DD  
DD  
SDRAM4  
SDRAM5  
SDRAM6  
SDRAM7  
SDRAM8  
8
SDRAM2  
SDRAM3  
SDRAM13  
SDRAM12  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
V
SDATA  
V
SS  
SS  
BUF_IN  
OE  
SMBus  
Decoding  
V
V
DD  
DD  
SDRAM9  
SDRAM4  
SDRAM5  
SDRAM11  
SDRAM10  
SCLOCK  
SDRAM10  
SDRAM11  
V
V
SS  
SS  
V
V
DD  
DD  
SDRAM12  
SDRAM13  
SDRAM14  
SDRAM15  
SDRAM6  
SDRAM7  
SDRAM9  
SDRAM8  
V
V
SS  
SS  
V
V
DD  
DD  
SDRAM16  
SDRAM17  
SDRAM16  
SDRAM17  
V
V
SS  
SS  
V
V
OE  
DDIIC  
SDATA  
SSIIC  
SCLOCK  
Pentium II is a registered trademark of Intel Corporation.  
Cypress Semiconductor Corporation  
Document #: 38-07217 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised December 4, 2001  

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