Datasheet > CY23EP09

CY23EP09

更新时间： 2024-11-18 04:37:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	355K
描述
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer

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CY23EP09 数据手册

CY23EP09

2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output

Zero Delay Buffer

Features

Functional Description

• 10 MHz to 220 MHz maximum operating range

The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed

to distribute high-speed clocks and is available in a 16-pin

SOIC or TSSOP package. The -1H version operates up to 220

(200) MHz frequencies at 3.3V (2.5V), and has higher drive

than the -1 devices. All parts have on-chip PLLs that lock to an

input clock on the REF pin. The PLL feedback is on-chip and

is obtained from the CLKOUT pad.

• Zero input-output propagation delay, adjustable by

loading on CLKOUT pin

• Multiple low-skew outputs

— 45 ps typical output-output skew

— One input drives nine outputs, grouped as 4 + 4 + 1

• 25 ps typical cycle-to-cycle jitter

• 15 ps typical period jitter

There are two banks of four outputs each, which can be

controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 2. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the

input clock to be directly applied to the outputs for chip and

system testing purposes.

• Standard and High drive strength options

• Available in space-saving 16-pin 150-mil SOIC or

4.4-mm TSSOP packages

The PLL enters a power-down mode when there are no rising

edges on the REF input (less than ~2 MHz). In this state, the

outputs are three-stated and the PLL is turned off, resulting in

less than 25 µA of current draw.

• 3.3V or 2.5V operation

• Industrial temperature available

In the special case when S2:S1 is 1:0, the PLL is bypassed

and REF is output from DC to the maximum allowable

frequency. The part behaves like a non-zero delay buffer in this

mode, and the outputs are not tri-stated.

The CY23EP09 is available in different configurations, as

shown in the Ordering Information table. The CY23EP09-1 is

the base part. The CY23EP09-1H is the high-drive version of

the -1, and its rise and fall times are much faster than the -1.

These parts are not intended for 5V input-tolerant applications

Pin Configuration

Block Diagram

CLKOUT

PLL

MUX

Top View

REF

CLKA1

CLKA2

REF

CLKOUT

CLKA1

CLKA4

CLKA3

V_DD

CLKA2

V_DD

CLKA3

CLKA4

GND

CLKB4

CLKB3

CLKB1

CLKB2

CLKB3

CLKB4

CLKB2

Select Input

Decoding

Cypress Semiconductor Corporation

Document #: 38-07760 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 5, 2005

12 3 4 5 6 7...13

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与CY23EP09相关器件

型号	品牌	获取价格	描述	数据表
CY23EP09_11	CYPRESS	获取价格	2.5 V or 3.3 V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXC-1	CYPRESS	获取价格	2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXC-1H	CYPRESS	获取价格	2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXC-1HT	CYPRESS	获取价格	2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXC-1T	CYPRESS	获取价格	2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXI-1	CYPRESS	获取价格	2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXI-1H	CYPRESS	获取价格	2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXI-1H	INFINEON	获取价格	2.5V or 3.3V,10- 220 MHz, Low Jitter, 9 Output Zero Delay Buffer
CY23EP09SXI-1HT	CYPRESS	获取价格	2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXI-1HT	INFINEON	获取价格	2.5V or 3.3V,10- 220 MHz, Low Jitter, 9 Output Zero Delay Buffer

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