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CY2318ANZPVXC-11 PDF预览

CY2318ANZPVXC-11

更新时间: 2024-09-06 21:12:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 138K
描述
Low Skew Clock Driver, 2318 Series, 18 True Output(s), 0 Inverted Output(s), PDSO48, LEAD FREE, SSOP-48

CY2318ANZPVXC-11 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.67系列:2318
输入调节:STANDARDJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:15.875 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.025 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:18最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:5 ns
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:2.794 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.5 mm
Base Number Matches:1

CY2318ANZPVXC-11 数据手册

 浏览型号CY2318ANZPVXC-11的Datasheet PDF文件第2页浏览型号CY2318ANZPVXC-11的Datasheet PDF文件第3页浏览型号CY2318ANZPVXC-11的Datasheet PDF文件第4页浏览型号CY2318ANZPVXC-11的Datasheet PDF文件第5页浏览型号CY2318ANZPVXC-11的Datasheet PDF文件第6页浏览型号CY2318ANZPVXC-11的Datasheet PDF文件第7页 
CY2318ANZ  
18 Output, 3.3V SDRAM Buffer for  
Desktop PCs with 4 DIMMs  
Functional Description  
Features  
• One input to 18 output buffer/driver  
• Supports up to four SDRAM DIMMs  
• Two additional outputs for feedback  
• Serial interface for individual output control  
• 150ps typical output-output skew  
• Up to 100 MHz operation  
The CY2318ANZ is a 3.3V buffer designed to distribute  
high-speed clocks in PC applications. The part has 18 outputs,  
16 of which can be used to drive up to four SDRAM DIMMs,  
and the remaining can be used for external feedback to a PLL.  
The device operates at 3.3V and outputs can run up to 100  
MHz, thus making it compatible with Pentium II® processors.  
The CY2318ANZ can be used in conjunction with the CY2280,  
CY2281, CY2282 or similar clock synthesizer for a complete  
Pentium II motherboard solution.  
• Dedicated OE pin for testing  
The CY2318ANZ also includes a serial interface which can  
enable or disable each output clock. On power-up, all output  
clocks are enabled (internal pull up). A separate Output  
Enable pin facilitates testing on ATE.  
• Space-saving 48-pin SSOP package  
• 3.3V operation  
Block Diagram  
Pin Configuration  
SSOP  
Top View  
1
NC  
NC  
VDD  
48  
47  
NC  
NC  
VDD  
SDRAM15  
SDRAM14  
VSS  
BUF_IN  
2
SDRAM0  
SDRAM1  
3
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
4
SDRAM0  
SDRAM1  
VSS  
VDD  
SDRAM2  
SDRAM3  
VSS  
BUF_IN  
VDD  
SDRAM4  
SDRAM5  
VSS  
VDD  
SDRAM6  
SDRAM7  
VSS  
VDD  
SDRAM16  
VSS  
5
SDRAM2  
SDRAM3  
6
7
VDD  
SDRAM4  
SDRAM5  
SDRAM6  
SDRAM7  
SDRAM8  
8
SDRAM13  
SDRAM12  
VSS  
OE  
VDD  
SDRAM11  
SDRAM10  
VSS  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
SDATA  
Serial Interface  
Decoding  
SDRAM9  
SCLOCK  
SDRAM10  
SDRAM11  
VDD  
SDRAM12  
SDRAM13  
SDRAM14  
SDRAM15  
SDRAM9  
SDRAM8  
VSS  
VDD  
SDRAM17  
VSS  
SDRAM16  
SDRAM17  
VDDIIC  
SDATA  
VSSIIC  
SCLOCK  
OE  
Cypress Semiconductor Corporation  
Document #: 38-07181 Rev. *C  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised Oct. 03, 2005  
[+] Feedback  

CY2318ANZPVXC-11 替代型号

型号 品牌 替代类型 描述 数据表
CY2318ANZPVXC-11T CYPRESS

完全替代

Low Skew Clock Driver, 2318 Series, 18 True Output(s), 0 Inverted Output(s), PDSO48, LEAD
CY29942AXI CYPRESS

功能相似

暂无描述
CY29940AXI CYPRESS

功能相似

2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer

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