Datasheet > CY14V101LA

CY14V101LA

更新时间： 2024-11-21 09:41:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
22页	886K
描述
1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles

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CY14V101LA 数据手册

CY14V101LA

CY14V101NA

1-Mbit (128 K × 8/64 K × 16) nvSRAM

1-Mbit (128

K × 8/64 K × 16) nvSRAM

Features

Functional Description

■ 25 ns and 45 ns access times

The Cypress CY14V101LA/CY14V101NA is a fast static RAM,

with a non-volatile element in each memory cell. The memory is

■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16

organized as 128 K bytes of 8 bits each or 64 K words of 16 bits

each. The embedded non-volatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

non-volatile memory. The SRAM provides infinite read and write

cycles, while independent non-volatile data resides in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

non-volatile elements (the STORE operation) takes place

automatically at power down. On power-up, data is restored to

the SRAM (the RECALL operation) from the non-volatile

memory. Both the STORE and RECALL operations are also

available under software control.

(CY14V101NA)

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap non-volatile elements initiated by

software, device pin, or AutoStore on power down

■ RECALL to SRAM initiated by software or power up

■ Infinite read, write, and recall cycles

■ 1 million STORE cycles to QuantumTrap

■ 20 year data retention

■ Core V_CC= 3.0 V to 3.6 V; I/O V_CCQ= 1.65 V to 1.95 V

■ Industrial temperature

■ 48-ball fine-pitch ball grid array (FBGA) package

■ Pb-free and restriction of hazardous substances (RoHS)

compliance

Logic Block Diagram ^{[1, 2, 3]}

V_CC

VCCQ

CAP

Quatrum Trap

1024 X 1024

A₅

A₆

A₇

A₈

A₉

POWER

CONTROL

STORE

RECALL

STORE/RECALL

CONTROL

HSB

STATIC RAM

ARRAY

1024 X 1024

A₁₂

A₁₃

A₁₄

SOFTWARE

DETECT

A₁₅

A₁₄- A₂

A₁₆

DQ₀

DQ₁

DQ₂

DQ₃

DQ₄

DQ₅

DQ₆

DQ₇

COLUMN I/O

DQ₈

DQ₉

DQ₁₀

COLUMN DEC

DQ₁₁

DQ₁₂

DQ₁₃

DQ₁₄

BLE

A₀A₁A₂A₃A₄A₁₀A₁₁

DQ₁₅

BHE

Notes

1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.

2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.

3. BHE and BLE are applicable for × 16 configuration only.

Cypress Semiconductor Corporation

Document #: 001-53953 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 4, 2011

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与CY14V101LA相关器件

型号	品牌	获取价格	描述	数据表
CY14V101LA-BA25XI	CYPRESS	获取价格	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
CY14V101LA-BA25XI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V101LA-BA25XIT	CYPRESS	获取价格	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
CY14V101LA-BA25XIT	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V101LA-BA45XI	CYPRESS	获取价格	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
CY14V101LA-BA45XI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V101LA-BA45XIT	CYPRESS	获取价格	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
CY14V101LA-BA45XIT	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V101NA	CYPRESS	获取价格	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
CY14V101NA-BA25XI	CYPRESS	获取价格	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles

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