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CY14V101PS-SF108XI PDF预览

CY14V101PS-SF108XI

更新时间: 2024-09-30 20:00:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
67页 1106K
描述
Non-Volatile SRAM, 128KX8, CMOS, PDSO16, SOIC-16

CY14V101PS-SF108XI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:2.27Samacsys Description:CYPRESS SEMICONDUCTOR - CY14V101PS-SF108XI - NV SRAM, 1MBIT, SOIC-16
JESD-30 代码:R-PDSO-G16长度:10.2865 mm
内存密度:1048576 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8功能数量:1
端子数量:16字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:2.667 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.4925 mmBase Number Matches:1

CY14V101PS-SF108XI 数据手册

 浏览型号CY14V101PS-SF108XI的Datasheet PDF文件第2页浏览型号CY14V101PS-SF108XI的Datasheet PDF文件第3页浏览型号CY14V101PS-SF108XI的Datasheet PDF文件第4页浏览型号CY14V101PS-SF108XI的Datasheet PDF文件第5页浏览型号CY14V101PS-SF108XI的Datasheet PDF文件第6页浏览型号CY14V101PS-SF108XI的Datasheet PDF文件第7页 
CY14V101PS  
1-Mbit (128K × 8) Quad SPI nvSRAM with  
Real Time Clock  
Temperature range  
Industrial: –40 °C to 85 °C  
Features  
Density  
1 Mbit (128K × 8)  
Packages  
16-pin SOIC  
Bandwidth  
108-MHz high-speed interface  
Read and write at 54 MBps  
Functional Overview  
The Cypress CY14V101PS combines a 1-Mbit nvSRAM with a  
QPI interface. The QPI allows writing and reading the memory in  
either a single (one I/O channel for one bit per clock cycle), dual  
(two I/O channels for two bits per clock cycle), or quad (four I/O  
channels for four bits per clock cycle) through the use of selected  
opcodes.  
Serial Peripheral Interface  
Clock polarity and phase modes 0 and 3  
Multi I/O option – Single SPI (SPI), Dual SPI (DPI), and Quad  
SPI (QPI)  
High reliability  
Infinite read, write, and RECALL cycles  
One million STORE cycles to nonvolatile elements (SONOS  
FLASH Quantum trap)  
The memory is organized as 128 Kbytes each consisting of  
SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The  
SRAM provides infinite read and write cycles, while the  
nonvolatile cells provide highly reliable storage of data. Data  
transfers from SRAM to the nonvolatile cells (STORE operation)  
take place automatically at power-down. On power-up, data is  
restored to the SRAM from the nonvolatile cells (RECALL  
operation). The user can initiate the STORE and RECALL  
operations through SPI instructions.  
Data retention: 20 years at 85 °C  
Read  
Commands: Standard, Fast, Dual I/O, and Quad I/O  
Modes: Burst Wrap, Continuous (XIP)  
Write  
Commands: Standard, Fast, Dual I/O, and Quad I/O  
Modes: Burst Wrap  
Data protection  
Hardware: Through Write Protect Pin (WP)  
Software: Through Write Disable instruction  
Block Protection: Status Register bits to control protection  
Special instructions  
STORE/RECALL: Transfer data between SRAM and  
Quantum Trap nvSRAM  
Serial Number: 8-byte customer selectable (OTP)  
Identification Number: 4-byte Manufacturer ID and Product  
ID  
Store from SRAM to nonvolatile SONOS FLASHQuantum Trap  
AutoStore: Initiated automatically at power-down with a small  
capacitor (VCAP  
)
Software: Using SPI instruction (STORE)  
Hardware: HSB pin  
Recall from nonvolatile SONOS FLASH Quantum Trap to  
SRAM  
Auto RECALL: Initiated automatically at power-up  
Software: Using SPI instruction (RECALL)  
Low-power modes  
Sleep: Average current = 380 µA at 85 °C  
Hibernate: Average current = 8 µA at 85 °C  
Operating supply voltages  
Core VCC: 2.7 V to 3.6 V  
I/O VCCQ: 1.71 V to 2.0 V  
Cypress Semiconductor Corporation  
Document Number: 001-94176 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 24, 2017  
 

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