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CY14V101Q3-SFXI PDF预览

CY14V101Q3-SFXI

更新时间: 2023-09-03 20:30:22
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
24页 1075K
描述
nvSRAM (non-volatile SRAM)

CY14V101Q3-SFXI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP, SOP16,.4Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:2.32
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:10.2865 mm内存密度:1048576 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
混合内存类型:N/A湿度敏感等级:3
功能数量:1端子数量:16
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:1.8,3.3 V
认证状态:Not Qualified座面最大高度:2.667 mm
最大待机电流:0.005 A子类别:SRAMs
最大压摆率:0.01 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN (800)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.4925 mmBase Number Matches:1

CY14V101Q3-SFXI 数据手册

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CY14V101Q3  
1 Mbit (128 K × 8) Serial SPI nvSRAM  
Low power consumption  
Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V  
Average active current of 10 mA at 30 MHz operation  
Features  
1-Mbit nonvolatile static random access memory (nvSRAM)  
Internally organized as 128 K × 8  
Industry standard configurations  
Industrial temperature  
16-pin small outline integrated circuit (SOIC) package  
Restriction of hazardous substances (RoHS) compliant  
STORE to QuantumTrap nonvolatile elements initiated  
automatically on power-down (AutoStore) or by user using  
HSB pin (Hardware STORE) or SPI instruction (Software  
STORE)  
RECALL to SRAM initiated on power-up  
(Power-Up RECALL) or by SPI instruction  
(Software RECALL)  
Functional Overview  
The Cypress CY14V101Q3 combines a 1 Mbit nvSRAM with a  
nonvolatile element in each memory cell with serial SPI interface.  
The memory is organized as 128 K words of 8 bits each. The  
embedded nonvolatile elements incorporate the QuantumTrap  
technology, creating the world’s most reliable nonvolatile  
memory. The SRAM provides infinite read and write cycles, while  
the QuantumTrap cell provides highly reliable nonvolatile  
storage of data. Data transfers from SRAM to the nonvolatile  
elements (STORE operation) takes place automatically at  
power-down. On power-up, data is restored to the SRAM from  
the nonvolatile memory (RECALL operation). Both STORE and  
RECALL operations can also be initiated by the user through SPI  
instruction.  
Automatic STORE on power-down with a small capacitor  
High reliability  
Infinite read, write, and RECALL cycles  
1 million STORE cycles to QuantumTrap  
Data retention: 20 years  
High speed serial peripheral interface (SPI)  
30 MHz clock rate  
Supports SPI mode 0 (0,0) and mode 3 (1,1)  
Write protection  
Hardware protection using Write Protect (WP) pin  
Software protection using Write Disable instruction  
Software block protection for 1/4,1/2, or entire array  
For a complete list of related documentation, click here.  
VCC VCCQ  
VCAP  
Logic Block Diagram  
Quantum Trap  
128 K X 8  
Power Control  
CS  
WP  
SCK  
Instruction decode  
Write protect  
Control logic  
STORE/RECALL  
Control  
STORE  
HSB  
SRAM ARRAY  
HOLD  
RECALL  
128 K X 8  
Instruction  
register  
D0-D7  
A0-A16  
Address  
Decoder  
Data I/O register  
Status register  
SO  
SI  
Cypress Semiconductor Corporation  
Document #: 001-67191 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 13, 2014  

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