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CY14V101QS-SE108XI PDF预览

CY14V101QS-SE108XI

更新时间: 2024-02-27 19:47:46
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
60页 1031K
描述
Non-Volatile SRAM, 128KX8, CMOS, PDSO16, SOIC-16

CY14V101QS-SE108XI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:2.27JESD-30 代码:R-PDSO-G16
长度:10.2865 mm内存密度:1048576 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
功能数量:1端子数量:16
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL座面最大高度:2.667 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.4925 mm
Base Number Matches:1

CY14V101QS-SE108XI 数据手册

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PRELIMINARY  
CY14V101QS  
1-Mbit (128K × 8) Quad SPI nvSRAM  
Recall from nonvolatile SONOS FLASH Quantum Trap to  
SRAM  
Features  
Density  
1 Mbit (128K × 8)  
Auto RECALL: Initiated automatically at power-up  
Software: Using SPI instruction (RECALL)  
Bandwidth  
Low-power modes  
108-MHz high-speed interface  
Read and write at 54 Mbps  
Sleep: Average current = 280 µA at 85 °C, 500 µA at 105 °C  
Hibernate: Average current = 8 µA at 85 °C, 10 µA at 105 °C  
Serial Peripheral Interface  
Clock polarity and phase modes 0 and 3  
Operating supply voltages  
Core VCC: 2.7 V to 3.6 V  
Multi I/O option – Single SPI (SPI), Dual SPI (DPI), and Quad  
I/O VCCQ: 1.71 V to 2.0 V  
SPI (QPI)  
Temperature range  
Extended Industrial: –40 °C to 105 °C  
Industrial: –40 °C to 85 °C  
High reliability  
Infinite read, write, and RECALL cycles  
One million STORE cycles to nonvolatile elements (SONOS  
FLASH Quantum trap)  
Packages  
16-pin SOIC  
24-ball FBGA  
Data retention: 20 years at 85 °C  
Read  
Commands: Normal, Fast, Dual I/O, and Quad I/O  
Modes: Burst Wrap, Continuous (XIP)  
Functional Overview  
Write  
The Cypress CY14V101QS combines a 1-Mbit nvSRAM in a  
monolithic integrated circuit with a QPI interface. The QPI allows  
writing and reading the memory in either a single (one I/O  
channel for one bit per clock cycle), dual (two I/O channels for  
two bits per clock cycle), or quad (four I/O channels for four bits  
per clock cycle) through the use of selected opcodes.  
Commands: Normal, Fast, Dual I/O, and Quad I/O  
Modes: Burst Wrap, Continuous (XIP)  
Data protection  
Hardware: Through Write Protect Pin (WP)  
Software: Through Write Disable instruction  
Block Protection: Status Register bits to control protection  
The memory is organized as 128K words of eight bits each  
consisting of SRAM and nonvolatile SONOS FLASH Quantum  
Trap cells. The SRAM provides infinite read and write cycles,  
while the nonvolatile cells provide highly reliable nonvolatile  
storage of data. Data transfers from SRAM to the nonvolatile  
cells (STORE operation) take place automatically at  
power-down. On power-up, data is restored to the SRAM from  
the nonvolatile cells (RECALL operation). You can also initiate  
the STORE and RECALL operations through SPI instruction.  
Special instructions  
STORE/RECALL: Access data between SRAM and  
Quantum Trap  
Serial Number: 8-byte customer selectable (OTP)  
Identification Number: 4-byte Manufacturer ID and Product  
ID  
Store from SRAM to nonvolatile SONOS FLASHQuantum Trap  
AutoStore: Initiated automatically at power-down with a small  
capacitor (VCAP  
)
Software: Using SPI instruction (STORE)  
Hardware: HSB pin  
Errata: For information on silicon errata, see “Errata” on page 55. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 001-85257 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 24, 2015  

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