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CN8223EPF

更新时间： 2024-09-17 03:26:11
品牌 Logo 应用领域
科胜讯 - CONEXANT 电信集成电路异步传输模式ATM
页数 文件大小 规格书
161页 1722K
描述
ATM Transmitter/Receiver with UTOPIA Interface

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中文翻译

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CN8223EPF 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP, QFP160,1.2SQ
针数：160Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N应用程序：ATM;SDH;SONET
JESD-30 代码：S-PQFP-G160JESD-609代码：e0
长度：28 mm功能数量：1
端子数量：160最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP160,1.2SQ
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：4.2 mm
子类别：ATM/SONET/SDH ICs标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：ATM/SONET/SDH TRANSCEIVER温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
Base Number Matches：1

CN8223EPF 数据手册

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CN8223  
ATM Transmitter/Receiver with UTOPIA Interface  
The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a  
single-access ATM service termination for User-to-Network (UNI) and  
Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI  
Specification 94/0317; Bellcore Specifications TR-TSV-000772, TR-TSV-000773,  
TR-NWT-000253, and T1S1/92-185; ITU Recommendations I.432, G.707, G.751,  
G.832, and Q.921; and ETSI prETS 300 213 and 300 214. Both Customer Premise  
Equipment (CPE) and switching system interface functions are provided. The CN8223  
provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (and STM-1) ATM cell alignment  
functions. The system interface is via a parallel FIFO port or UTOPIA interface. In  
addition, the CN8223 terminates the operations and maintenance flows F1, F2, and F3.  
The CN8223 provides four FIFO port interfaces and one UTOPIA interface. Each  
receiver port can be programmed with a particular Virtual Channel Identifier/Virtual  
Path Identifier (VCI/VPI) address for message routing. VCI/VPI pages can also be  
selected via masking registers.  
Distinguishing Features  
•
Integrates 7 line framers with ATM  
layer processing according to ATM  
Forum UNI and NNI Specifications  
•
•
UTOPIA Level 1 interface  
Internal framers for DS3, E3 (G.751,  
G.832), E4 (G.832), STS-1, STS-3c,  
STM-1  
•
•
PLCP and G.804 HEC cell alignment  
for all data rates from 1.544 Mbps to  
155 Mbps  
Direct interface to TAXITM or external  
T1/E1 framers  
•
•
ATM and SMDS cell modes  
4 FIFO ports with header screening,  
formatting, and transmit priority  
controls  
The microprocessor can set control registers for insertion of selected header fields  
by the transmitter on an individual port basis. The microprocessor can also control  
insertion of all overhead and can insert errors in selected fields for test equipment  
applications.  
•
•
Idle cells generated and screened  
Statistics counts latched on  
one-second intervals  
•
•
Error detection and insertion  
Option insertion or generation of all  
line and cell overhead  
Functional Block Diagram  
•
•
Serial or parallel line interface  
Available evaluation module  
reference design and software  
Microprocessor Microprocessor  
Address  
Data  
Line Overhead  
•
Supports Automatic Protection  
Switching (APS)  
7
8
16  
8
HDLC  
Data  
Link  
Data  
Bus  
Cell  
FIFO  
8
Microprocessor  
Interface  
52 Control Registers  
28 Status Registors  
4-Port  
FIFO  
Interface  
Applications  
•
•
•
•
WAN equipment  
ATM switches  
Test equipment  
ATM routers and hub  
Port  
Control  
8
UTOPIA  
or FIFO  
Interface  
8
Framers  
1
TX  
Rate  
Control  
DS3  
Cell  
Generation  
8
E3 (G.751)  
E3 (G.832)  
STS-1  
Cell  
Alignment  
ATM  
UNI  
E4 (G.832)  
HEC or  
PLCP  
8
8
Cell  
Validation  
STS-3c  
STM-1  
TAXI  
1
Header  
Filter  
8
ATM Layer  
Physical Framing  
Data Sheet  
100046C  
March 8, 2000  
1234567...161

中文翻译

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