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CN8330EPJD PDF预览

CN8330EPJD

更新时间： 2024-09-16 21:55:43
品牌 Logo 应用领域
科胜讯 - CONEXANT 电信集成电路控制器
页数 文件大小 规格书
101页 571K
描述
DS3/E3 Framer with 52 Mbps HDLC Controller

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中文翻译

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CN8330EPJD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：QCCJ, LDCC68,1.0SQ
针数：68Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：S-PQCC-J68JESD-609代码：e0
长度：24.23 mm功能数量：1
端子数量：68最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC68,1.0SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：5 V认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Digital Transmission Controllers
最大压摆率：0.175 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：FRAMER温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：24.23 mm

CN8330EPJD 数据手册

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CN8330  
DS3/E3 Framer with 52 Mbps HDLC Controller  
The CN8330 is an integral DS3/E3 framer designed to support the transmission  
formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751  
standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T  
PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a  
High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing  
overhead.  
The CN8330 provides framing recovery for M13, C-bit parity, Syntran, and G.751  
E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be  
enabled to reduce jitter on the incoming data. Transmit and receive data is available to  
the host in either serial or parallel byte and nibble formats. Access is provided to the  
terminal data link and the Far End Alarm/Control (FEAC) channel, as specified in  
T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations  
(LCVs), parity errors, and Far End Block Errors (FEBEs).  
Distinguishing Features  
•
•
Supports DS3/E3 framing modes  
Includes high-speed HDLC controller  
(52 MHz)  
•
•
•
Framing recovery for M13, C-bit  
parity, Syntran, and G.751 E3 signals  
Serial or parallel (octet or nibble)  
interface modes  
Average reframe time of less than  
1 ms for DS3 and less than 250 µs  
for E3  
•
Supports the LAPD terminal data link  
and FEAC channel as defined in  
T1.107a-1989  
Two operational modes are available: microprocessor and stand-alone monitor  
control modes. The microprocessor control mode monitors all status conditions and  
provides configuration control. The stand-alone monitor mode allows the CN8330 to  
operate as a monitor providing status and alarm information on external pins.  
•
•
•
68-pin PLCC or 80-pin MQFP  
surface-mount package  
Operates from a single +5 VDC ±5%  
power supply  
Low-power CMOS technology  
Functional Block Diagram  
Applications  
•
•
•
•
•
•
•
Digital PCM switches  
Digital Cross-Connect Systems  
Channel Service Units (CSUs)  
Channel extenders  
ATM Switches/Concentrators  
PBXs  
Switched Multimegabit Digital  
Service (SMDS) Equipment  
Test equipment  
Bypass  
RXPOS  
RXNEG  
DS3CKI  
RXMSY  
CBITO  
Unipolar  
Conversion  
FIFO  
M
U
X
Framing  
Recovery  
RXCCK  
TXCKI  
RXDAT  
RXCLK  
FIFO  
Enable  
•
•
Routers (including HSSI ports)  
Overhead/  
Data Link  
Processing  
Status  
Source  
Loopback  
RDAT[7:0]  
RXBCK  
Status  
PPDL  
Receiver  
M
U
X
TXPOS  
TXNEG  
TCLKO  
TXBCK  
Framing/  
Overhead  
Insertion  
PPDL  
Transmitter  
Bipolar  
Encoder  
TDAT[7:0]  
Overhead/  
Data Link  
Processing  
TXCCK  
CBITI  
Line  
Loopback  
TXCKI  
TXDATI  
TXSYI  
AD[7:0]  
Control  
To/From  
All Blocks  
Microprocessor  
Interface  
Data Sheet  
100441E  
October 13, 1999  
1234567...101

中文翻译

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