Advance Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Distinguishing Features
Product Description
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256-, 128-, 64-, or 32-channel HDLC
controller
The CN8478, CN8474A, CN8472A, and CN8471A are advanced Multichannel
Synchronous Communication Controllers (MUSYCCs) that format and deformat up
to 256 (CN8478), 128 (CN8474A), 64 (CN8472A), or 32 (CN8471A) HDLC
channels in a single CMOS integrated circuit. MUSYCC operates at Layer 2 of the
Open Systems Interconnection (OSI) protocol reference model. MUSYCC provides
a comprehensive, high-density solution for processing HDLC channels for
internetworking applications such as Frame Relay, ISDN D-channel signaling,
X.25, Signaling System 7 (SS7), DXI, ISUP, and LAN/WAN data transport. Under
minimal host supervision, MUSYCC manages a linked list of channel data buffers
in host memory by performing Direct Memory Access (DMA) of the HDLC
channels.
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OSI Layer 2 protocol support
General purpose HDLC (ISO 3309)
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X.25 (LAPB)
Frame relay (LAPF/ANSI T1.618)
ISDN D-channel (LAPD/Q.921)
SS7 support
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8, 4, 2, or 1 independent serial interfaces
which support
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T1/E1 data streams
DC to 8.192 Mbps TDM busses
Configurable logical channels
MUSYCC interfaces with eight independent serial data streams, such as T1/E1
signals, and then transfers data across the popular 32-bit Peripheral Component
Interface (PCI) bus to system memory at a rate of up to 66 MHz. Each serial
interface can be operated at up to 8.192 MHz. Logical channels can be mapped as
any combination of DS0 time slots to support ISDN hyperchannels (Nx64 kbps) or
as any number of bits in a DS0 for subchanneling applications (Nx8 kbps).
MUSYCC also includes a 32-bit expansion port for bridging the PCI bus to local
microprocessors or peripherals. A JTAG port enables boundary-scan testing to
replace bed-of-nails board testing.
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Standard DS0 (56, 64 kbps)
Hyperchannel (Nx64)
Subchannel (Nx8)
Per-channel protocol mode selection
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16-bit FCS mode
32-bit FCS mode
SS7 mode (16-bit FCS)
Transparent mode (unformatted data)
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Per-channel DMA buffer management
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Linked list data structures
Device drivers for Linux, VxWorks®, and pSOS™ operating systems are
available under a no-fee license agreement from Conexant. The device drivers
include C source code and supporting software documents.
Variable size transmit/receive FIFO
Per-channel message length check
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Select no length checking
Select from two 12-bit registers to
compare message length
Maximum length 16,384 Bytes
Functional Block Diagram
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Direct PCI bus interface
Channel Group 0 – Serial Interface
Host
Interface
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32-bit, 66 or 33 MHz operation
Bus master and slave operation
PCI Version 2.1
DMA
Controller
Tx/Rx-DMAC
Bit-Level
Processor
Tx/Rx-BLP
Port
Interface
Tx/Rx
Interrupt
Controller
Local Expansion Bus interface (EBUS)
Device
Configuration
Registers
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32-bit multiplexed address/data bus
Burst access up to 64 Bytes
Channel Group 1 – Serial Interface
Channel Group 2 – Serial Interface
Channel Group 3 – Serial Interface
Channel Group 4 – Serial Interface
Channel Group 5 – Serial Interface
Channel Group 6 – Serial Interface
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Low power, 3.3/2.5 V CMOS operation
JTAG boundary scan access port
208-pin PQFP/surface-mount package
BGA
PCI
Interface
Applications
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ISDN basic-rate or primary-rate interfaces
ISDN D-channel controller
Routers
Cellular base station switch controller
CSU/DSU
Protocol converter
Packet data switch
Frame relay switches/Frame Relay Access
Devices (FRAD)
PCI
Configuration
Space
(Function 0)
Channel Group 7 – Serial Interface
Note: Number of serial interfaces is device-dependent.
PCI
Configuration
Space
Boundary Scan and Test Access
Expanion Bus Interface
(Function 1)
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DXI network interface
Distributed packet-based communications
system
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Access multiplexer/concentrator
100660E
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