Datasheet > CDCV850IDGGRG4

CDCV850IDGGRG4

更新时间： 2024-11-23 14:48:27

品牌	Logo	应用领域
德州仪器 - TI		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
20页	809K
描述
2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85

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CDCV850IDGGRG4 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP48,.3,20	针数：	48
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	系列：	850
输入调节：	DIFFERENTIAL	JESD-30 代码：	R-PDSO-G48
长度：	12.5 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.012 A	功能数量：	1
反相输出次数：		端子数量：	48
实输出次数：	10	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP48,.3,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5,2.5/3.3 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.075 ns	座面最大高度：	1.2 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	6.1 mm
Base Number Matches：	1

CDCV850IDGGRG4 数据手册

CDCV850

2.5-V PHASE LOCK LOOP CLOCK DRIVER

WITH 2-LINE SERIAL INTERFACE

SCAS647D − OCTOBER 2000 − REVISED APRIL 2013

DGG PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Driver for Double

Data-Rate Synchronous DRAM

Applications

GND

V_DDQ

GND

V_DDQ

Spread Spectrum Clock Compatible

Operating Frequency: 60 to 140 MHz

Low Jitter (cyc−cyc): 75 ps

Distributes One Differential Clock Input to

Ten Differential Outputs

43 Y6

GND

42 GND

41 GND

40 Y7

Two-Line Serial Interface Provides Output

Enable and Functional Control

Outputs Are Put Into a High-Impedance

State When the Input Differential Clocks

Are <20 MHz

V_DDQ

SCLK

CLK

V_DDI

AV_DD

AGND

GND

V_DDQ

GND

V_DDQ

SDATA

FBIN

V_DDQ

FBOUT

GND

V_DDQ

GND

48-Pin TSSOP Package

Consumes <250-μA Quiescent Current

External Feedback Pins (FBIN, FBIN) Are

Used to Synchronize the Outputs to the

Input Clocks

description

The CDCV850 is a high-performance, low-skew,

low-jitter zero delay buffer that distributes a

differential clock input pair (CLK, CLK) to ten

differential pairs of clock outputs (Y[0:9], Y[0:9])

and one differential pair of feedback clock outputs

(FBOUT, FBOUT). The clock outputs are con-

trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,

SCLK), and the analog power input (AV ). A two-line serial interface can put the individual output clock pairs

in a high-impedance state. When the AV terminal is tied to GND, the PLL is turned off and bypassed for test

purposes.

The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation

is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line

serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ).

Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to

enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit

is written to the control register. The registers must be accessed in sequential order (i.e., random access of the

registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in

applications where this programming option is not required (after power up, all output pairs will then be enabled).

When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),

the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low

power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up, as well as changes to various 2-line serial registers that

affect the PLL. The CDCV850 is characterized in a temperature range from −40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...20

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CDCV850IDGGRG4 替代型号

型号	品牌	替代类型	描述	数据表
CDCV850IDGGR	TI	完全替代	2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 t

与CDCV850IDGGRG4相关器件

型号	品牌	获取价格	描述	数据表
CDCV855	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855I	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855IPW	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855IPWR	TI	获取价格	暂无描述
CDCV855PW	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855PWR	TI	获取价格	1:4 DDR PLL clock driver 28-TSSOP 0 to 70
CDCV857	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857_08	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857A	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857AGQLR	TI	获取价格	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applicatio

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