CDCV855IPWR

更新时间： 2024-11-26 13:06:47

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
10页	140K
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CDCV855IPWR 数据手册

CDCV855, CDCV855I

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002

PW PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Driver for Double

Data-Rate Synchronous DRAM

Applications

GND

Spread Spectrum Clock Compatible

Operating Frequency: 60 MHz to 180 MHz

Low Jitter (cyc–cyc): ±50 ps

DDQ

GND

PWRDWN

Distributes One Differential Clock Input to

Four Differential Clock Outputs

CLK

23 FBIN

22 FBIN

Enters Low Power Mode and Three-State

Outputs When Input CLK Signal Is Less

Than 20 MHz or PWRDWN Is Low

DDQ

20 FBOUT

AGND

FBOUT

Operates From Dual 2.5-V Supplies

28-Pin TSSOP Package

DDQ

Consumes < 200-µA Quiescent Current

External Feedback PIN (FBIN, FBIN) Are

Used to Synchronize the Outputs to the

Input Clocks

GND

description

The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock

input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of

feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency

with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is

shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below

a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit

detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the

PLL again and enables the outputs.

When AV

is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able

to track spread spectrum clocking for reduced EMI.

Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV855 is characterized for both commercial and

industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGED DEVICES

TSSOP (PW)

CDCV855PW

CDCV855IPW

0°C to 70°C

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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CDCV855IPWR 替代型号

型号	品牌	替代类型	描述	数据表
CDCV855IPW	TI	完全替代	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855PWR	TI	类似代替	1:4 DDR PLL clock driver 28-TSSOP 0 to 70
CDCV855PW	TI	类似代替	2.5-V PHASE-LOCK LOOP CLOCK DRIVER

与CDCV855IPWR相关器件

型号	品牌	获取价格	描述	数据表
CDCV855PW	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855PWR	TI	获取价格	1:4 DDR PLL clock driver 28-TSSOP 0 to 70
CDCV857	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857_08	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857A	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857AGQLR	TI	获取价格	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applicatio
CDCV857B	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BDGG	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BDGGG4	TI	获取价格	2.5 V Phase Lock Loop DDR Clock Driver 48-TSSOP 0 to 70
CDCV857BDGGR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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