CDCV857B

更新时间： 2024-11-17 22:40:11

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
14页	276K
描述
2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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数据手册
替代型号

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CDCV857B 数据手册

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SCAS689 − FEBRUARY 2003

Phase-Lock Loop Clock Driver for Double

Data-Rate Synchronous DRAM

Applications

Enters Low-Power Mode When No CLK

Input Signal Is Applied or PWRDWN Is Low

Operates From Dual 2.5-V Supplies

Spread Spectrum Clock Compatible

Operating Frequency: 60 MHz to 200 MHz

Low Jitter (cycle-cycle): 50 ps

Low Static Phase Offset: 50 ps

Low Jitter (Period): 35 ps

Available in a 48-Pin TSSOP Package or

56-Ball MicroStar Junior BGA Package

Consumes < 100-µA Quiescent Current

External Feedback Pins (FBIN, FBIN) Are

Used to Synchronize the Outputs to the

Input Clocks

Distributes One Differential Clock Input to

10 Differential Outputs

Meets/Exceeds the Latest DDR JEDEC

Spec JESD82−1

description

The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock

input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback

clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback

clocks (FBIN, FBIN), and the analog power input (AV ). When PWRDWN is high, theoutputs switch in phase

and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)

and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input

frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input

frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this

detection circuit turns the PLL on and enables the outputs.

When AV is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able

to track spread spectrum clocking for reduced EMI.

Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV857B is characterized for both commercial and

industrial temperature ranges.

AVAILABLE OPTIONS

TSSOP (DGG)

CDCV857BDGG

CDCV857BIGG

MicroStar Junior BGA (GQL)

0°C to 85°C

CDCV857BGQL

—

−40°C to 85°C

FUNCTION TABLE

(Select Functions)

INPUTS

PWRDWN

OUTPUTS

PLL

CLK

Y[0:9]

FBOUT

GND

Bypassed/Off

GND

Bypassed/Off

Off

2.5 V (nom)

<20 MHz <20 MHz

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior is a trademark of Texas Instruments Incorporated.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...14

中文翻译

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CDCV857B 替代型号

型号	品牌	替代类型	描述	数据表
CDCV857A	TI	功能相似	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857	TI	功能相似	2.5-V PHASE LOCK LOOP CLOCK DRIVER

与CDCV857B相关器件

型号	品牌	获取价格	描述	数据表
CDCV857BDGG	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BDGGG4	TI	获取价格	2.5 V Phase Lock Loop DDR Clock Driver 48-TSSOP 0 to 70
CDCV857BDGGR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BDGGRG4	TI	获取价格	2.5 V Phase Lock Loop DDR Clock Driver 48-TSSOP 0 to 70
CDCV857BGQL	TI	获取价格	857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56, PLAST
CDCV857BGQLR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BI	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BIDGG	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BIDGGR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BIDGGRG4	TI	获取价格	CDCV857B, CDCV857BI 2.5-V Phase-Lock Loop Clock Driver 48-TSSOP -40 to 85

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