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CDCV857DGGG4 PDF预览

CDCV857DGGG4

更新时间： 2024-11-18 14:49:23
品牌 Logo 应用领域
德州仪器 - TI 驱动双倍数据速率光电二极管逻辑集成电路
页数 文件大小 规格书
14页 349K
描述
1:10 DDR Phase-Lock Loop Clock Driver 48-TSSOP 0 to 70

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CDCV857DGGG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.29系列：857
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：2功能数量：1
反相输出次数：端子数量：48
实输出次数：10最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5 V传播延迟（tpd）：4.5 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.075 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mm最小 fmax：200 MHz
Base Number Matches：1

CDCV857DGGG4 数据手册

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CDCV857  
2.5-V PHASE LOCK LOOP CLOCK DRIVER  
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000  
DGG PACKAGE  
(TOP VIEW)  
Phase-Lock Loop Clock Driver for Double  
Data-Rate Synchronous DRAM  
Applications  
GND  
Y0  
GND  
Y5  
1
48  
47  
46  
45  
44  
Spread Spectrum Clock Compatible  
Operating Frequency: 60 to 200 MHz  
Low Jitter (cyc–cyc): ±75 ps  
2
Y0  
Y5  
3
V
V
4
DDQ  
Y1  
DDQ  
Y6  
5
Distributes One Differential Clock Input to  
Ten Differential Outputs  
Y1  
GND  
GND  
Y2  
6
43 Y6  
7
42 GND  
41 GND  
40 Y7  
Three-State Outputs When the Input  
Differential Clocks Are <20 MHz  
8
9
Operates From Dual 2.5-V Supplies  
48-Pin TSSOP Package  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Y2  
Y7  
V
V
DDQ  
DDQ  
Consumes < 200-µA Quiescent Current  
V
PWRDWN  
FBIN  
DDQ  
CLK  
External Feedback PIN (FBIN, FBIN) Are  
Used to Synchronize the Outputs to the  
Input Clocks  
CLK  
FBIN  
V
V
DDQ  
DDQ  
AV  
FBOUT  
FBOUT  
GND  
Y8  
DD  
description  
AGND  
GND  
Y3  
The CDCV857 is a high-performance, low-skew,  
low-jitter zero delay buffer that distributes a  
differential clock input pair (CLK, CLK) to ten  
differential pairs of clock outputs (Y[0:9], Y[0:9])  
and one differential pair of feedback clock output  
(FBOUT, FBOUT). The clock outputs are  
controlled by the clock inputs (CLK, CLK), the  
feedback clocks (FBIN, FBIN), and the analog  
Y3  
Y8  
V
V
DDQ  
Y4  
DDQ  
Y9  
Y4  
Y9  
GND  
GND  
power input (AV ). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When  
DD  
PWRDWNislow, alloutputsaredisabledtohighimpedancestate(3-state), andthePLLisshutdown(lowpower  
mode). The device also enters this low power mode when the input frequency falls below a suggested detection  
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low  
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and  
enables the outputs.  
When AV  
is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857 is also able  
DD  
to track spread spectrum clocking for reduced EMI.  
Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.  
This stabilization time is required following power up. The CDCV857 is characterized for operation from 0°C  
to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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