CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
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High-Performance 1:10 Clock Driver for
General-Purpose Applications. Operates up to
200 MHz at VDD 3.3 V
PW PACKAGE
(TOP VIEW)
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•
•
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Pin-to-Pin Skew < 100 ps at VDD 3.3 V
VDD Range: 2.3 V to 3.6 V
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
CLK
2
V
DD
V
V
DD
3
1Y0
1Y1
1Y2
GND
GND
1Y3
Operating Temperature Range –40°C to 85°C
Output Enable Glitch Suppression
DD
4
2Y0
2Y1
GND
GND
2Y2
2Y3
5
Distributes One Clock Input to Two Banks of
Five Outputs
6
7
8
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25-Ω On-Chip Series Damping Resistors
9
1Y4
Packaged in 24-Pin TSSOP
10
11
12
V
DD
V
V
DD
1G
2Y4
DD
2G
DESCRIPTION
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a
2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.