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CDCV855PWR PDF预览

CDCV855PWR

更新时间： 2024-11-18 13:06:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
10页 140K
描述
1:4 DDR PLL clock driver 28-TSSOP 0 to 70

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中文翻译

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CDCV855PWR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Not Recommended零件包装代码：SSOP
包装说明：TSSOP, TSSOP28,.25针数：28
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：6.98
Is Samacsys：N系列：855
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G28
JESD-609代码：e4长度：9.7 mm
负载电容（CL）：14 pF逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：28实输出次数：4
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP28,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：2.5 V传播延迟（tpd）：4.5 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm最小 fmax：180 MHz
Base Number Matches：1

CDCV855PWR 数据手册

 浏览型号CDCV855PWR的Datasheet PDF文件第2页浏览型号CDCV855PWR的Datasheet PDF文件第3页浏览型号CDCV855PWR的Datasheet PDF文件第4页浏览型号CDCV855PWR的Datasheet PDF文件第5页浏览型号CDCV855PWR的Datasheet PDF文件第6页浏览型号CDCV855PWR的Datasheet PDF文件第7页 
CDCV855, CDCV855I  
2.5-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002  
PW PACKAGE  
(TOP VIEW)  
D
Phase-Lock Loop Clock Driver for Double  
Data-Rate Synchronous DRAM  
Applications  
GND  
Y0  
GND  
Y3  
1
28  
27  
26  
25  
24  
D
D
D
D
Spread Spectrum Clock Compatible  
Operating Frequency: 60 MHz to 180 MHz  
Low Jitter (cyc–cyc): ±50 ps  
2
Y0  
Y3  
3
V
V
4
DDQ  
DDQ  
GND  
PWRDWN  
5
Distributes One Differential Clock Input to  
Four Differential Clock Outputs  
CLK  
CLK  
6
23 FBIN  
22 FBIN  
7
D
Enters Low Power Mode and Three-State  
Outputs When Input CLK Signal Is Less  
Than 20 MHz or PWRDWN Is Low  
V
8
21  
V
DDQ  
DDQ  
AV  
9
20 FBOUT  
DD  
10  
11  
12  
13  
14  
19  
18  
17  
16  
15  
AGND  
FBOUT  
D
D
D
D
Operates From Dual 2.5-V Supplies  
28-Pin TSSOP Package  
V
V
DDQ  
Y1  
DDQ  
Y2  
Consumes < 200-µA Quiescent Current  
Y1  
Y2  
External Feedback PIN (FBIN, FBIN) Are  
Used to Synchronize the Outputs to the  
Input Clocks  
GND  
GND  
description  
The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock  
input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of  
feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency  
with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is  
shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below  
a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit  
detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the  
PLL again and enables the outputs.  
When AV  
is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able  
DD  
to track spread spectrum clocking for reduced EMI.  
Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.  
This stabilization time is required following power up. The CDCV855 is characterized for both commercial and  
industrial temperature ranges.  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
T
A
TSSOP (PW)  
CDCV855PW  
CDCV855IPW  
0°C to 70°C  
–40°C to 85°C  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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CDCV855PWR 替代型号

型号 品牌 替代类型 描述 数据表
CDCV855PW TI

完全替代

 2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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