Datasheet > CDCV857_08

CDCV857_08

更新时间： 2024-11-19 02:58:39

品牌	Logo	应用领域
德州仪器 - TI		驱动
页数	文件大小	规格书
14页	349K
描述
2.5-V PHASE LOCK LOOP CLOCK DRIVER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CDCV857_08 数据手册

CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

DGG PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Driver for Double

Data-Rate Synchronous DRAM

Applications

GND

Spread Spectrum Clock Compatible

Operating Frequency: 60 to 200 MHz

Low Jitter (cyc–cyc): ±75 ps

DDQ

Distributes One Differential Clock Input to

Ten Differential Outputs

GND

43 Y6

42 GND

41 GND

40 Y7

Three-State Outputs When the Input

Differential Clocks Are <20 MHz

Operates From Dual 2.5-V Supplies

48-Pin TSSOP Package

DDQ

Consumes < 200-µA Quiescent Current

PWRDWN

FBIN

DDQ

CLK

External Feedback PIN (FBIN, FBIN) Are

Used to Synchronize the Outputs to the

Input Clocks

CLK

FBIN

DDQ

FBOUT

GND

description

AGND

GND

The CDCV857 is a high-performance, low-skew,

low-jitter zero delay buffer that distributes a

differential clock input pair (CLK, CLK) to ten

differential pairs of clock outputs (Y[0:9], Y[0:9])

and one differential pair of feedback clock output

(FBOUT, FBOUT). The clock outputs are

controlled by the clock inputs (CLK, CLK), the

feedback clocks (FBIN, FBIN), and the analog

DDQ

GND

power input (AV ). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When

PWRDWNislow, alloutputsaredisabledtohighimpedancestate(3-state), andthePLLisshutdown(lowpower

mode). The device also enters this low power mode when the input frequency falls below a suggested detection

frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low

frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and

enables the outputs.

When AV

is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857 is also able

to track spread spectrum clocking for reduced EMI.

Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV857 is characterized for operation from 0°C

to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...14

中文翻译

下载PDF

与CDCV857_08相关器件

型号	品牌	获取价格	描述	数据表
CDCV857A	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCV857AGQLR	TI	获取价格	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applicatio
CDCV857B	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BDGG	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BDGGG4	TI	获取价格	2.5 V Phase Lock Loop DDR Clock Driver 48-TSSOP 0 to 70
CDCV857BDGGR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BDGGRG4	TI	获取价格	2.5 V Phase Lock Loop DDR Clock Driver 48-TSSOP 0 to 70
CDCV857BGQL	TI	获取价格	857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56, PLAST
CDCV857BGQLR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857BI	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER

与CDCV857_08相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

18
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

43
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

38

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCV857_08

CDCV857_08 数据手册

与CDCV857_08相关器件

与CDCV857_08相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCV857_08

CDCV857_08 数据手册

与CDCV857_08相关器件

与CDCV857_08相关文章

您还可以找

您在本页遇到什么问题？