5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 触发器/锁存器> CD74AC109M96E4
CD74AC109M96E4 PDF预览

CD74AC109M96E4

更新时间： 2024-09-15 05:09:03
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 346K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

阅读下载

中文翻译

获取价格

CD74AC109M96E4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, MS-012AC, SOIC-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.19Is Samacsys：N
系列：ACJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：J-KBAR FLIP-FLOP
最大频率@ Nom-Sup：71000000 Hz最大I（ol）：0.012 A
湿度敏感等级：1位数：2
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3/5 V传播延迟（tpd）：129 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.5 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：100 MHzBase Number Matches：1

CD74AC109M96E4 数据手册

 浏览型号CD74AC109M96E4的Datasheet PDF文件第2页浏览型号CD74AC109M96E4的Datasheet PDF文件第3页浏览型号CD74AC109M96E4的Datasheet PDF文件第4页浏览型号CD74AC109M96E4的Datasheet PDF文件第5页浏览型号CD74AC109M96E4的Datasheet PDF文件第6页浏览型号CD74AC109M96E4的Datasheet PDF文件第7页 
CD54AC109, CD74AC109  
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS326 – JANUARY 2003  
CD54AC109 . . . F PACKAGE  
CD74AC109 . . . E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply Voltage  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1CLR  
1J  
V
CC  
2CLR  
2J  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
1K  
Balanced Propagation Delays  
1CLK  
1PRE  
1Q  
2K  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
2CLK  
11 2PRE  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
10  
9
1Q  
2Q  
2Q  
GND  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
description/ordering information  
The ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset  
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE  
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to  
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and  
isnotdirectlyrelatedtotherisetimeoftheclockpulse. Followingthehold-timeinterval, dataattheJandKinputs  
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle  
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
PDIP – E  
SOIC – M  
CDIP – F  
Tube  
CD74AC109E  
CD74AC109E  
AC109M  
–55°C to 125°C  
Tape and reel CD74AC109M96  
Tube CD54AC109F3A  
CD54AC109F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

与CD74AC109M96E4相关器件

型号 品牌 获取价格 描述 数据表
CD74AC109M96G4 TI

获取价格

 		DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
CD74AC109MX GE

获取价格

 		J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output,
CD74AC10E TI

获取价格

 		Triple 3-Input NAND Gate
CD74AC10E GE

获取价格

 		NAND Gate, AC Series, 3-Func, 3-Input, CMOS, PDIP14,
CD74AC10E ROCHESTER

获取价格

 		NAND Gate, AC Series, 3-Func, 3-Input, CMOS, PDIP14, PACKAGE-14
CD74AC10EE4 TI

获取价格

 		AC SERIES, TRIPLE 3-INPUT NAND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14
CD74AC10EE4 ROCHESTER

获取价格

 		NAND Gate, AC Series, 3-Func, 3-Input, CMOS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14
CD74AC10EN ETC

获取价格

 		Logic IC
CD74AC10EX RENESAS

获取价格

 		IC,LOGIC GATE,3 3-INPUT NAND,AC-CMOS,DIP,14PIN,PLASTIC
CD74AC10EX GE

获取价格

 		NAND Gate, AC Series, 3-Func, 3-Input, CMOS, PDIP14,

与CD74AC109M96E4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证