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BUK107-50GLT/R PDF预览

BUK107-50GLT/R

更新时间: 2024-11-13 12:59:39
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
9页 81K
描述
TRANSISTOR 0.5 A, 50 V, 0.2 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power

BUK107-50GLT/R 技术参数

生命周期:Obsolete包装说明:SMALL OUTLINE, R-PDSO-G4
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8541.29.00.75风险等级:5.84
Is Samacsys:N其他特性:LOGIC LEVEL COMPATIBLE, ESD PROTECTED
外壳连接:DRAIN配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:50 V最大漏极电流 (ID):0.5 A
最大漏源导通电阻:0.2 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PDSO-G4元件数量:1
端子数量:4工作模式:ENHANCEMENT MODE
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE极性/信道类型:N-CHANNEL
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:DUAL
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

BUK107-50GLT/R 数据手册

 浏览型号BUK107-50GLT/R的Datasheet PDF文件第2页浏览型号BUK107-50GLT/R的Datasheet PDF文件第3页浏览型号BUK107-50GLT/R的Datasheet PDF文件第4页浏览型号BUK107-50GLT/R的Datasheet PDF文件第5页浏览型号BUK107-50GLT/R的Datasheet PDF文件第6页浏览型号BUK107-50GLT/R的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
PowerMOS transistor  
Logic level TOPFET  
BUK107-50DL  
DESCRIPTION  
QUICK REFERENCE DATA  
Monolithic overload protected logic  
level power MOSFET in a surface  
mount plastic envelope, intended as  
a general purpose switch for  
automotive systems and other  
applications.  
SYMBOL  
PARAMETER  
MAX.  
50  
UNIT  
V
VDS  
ID  
Continuous drain source voltage  
Continuous drain current  
Total power dissipation  
0.7  
A
PD  
1.8  
W
APPLICATIONS  
Tj  
Continuous junction temperature  
Drain-source on-state resistance  
150  
200  
˚C  
General controller for driving  
lamps  
RDS(ON)  
m  
small motors  
solenoids  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Vertical power DMOS output  
stage  
Overload protected up to  
85˚C ambient  
DRAIN  
Overload protection by current  
limiting and overtemperature  
sensing  
O/V  
CLAMP  
Latched overload protection  
reset by input  
POWER  
INPUT  
MOSFET  
5 V logic compatible input level  
Control of power MOSFET  
and supply of overload  
protection circuits  
RIG  
LOGIC AND  
derived from input  
PROTECTION  
Low operating input current  
permits direct drive by  
micro-controller  
ESD protection on all pins  
Overvoltage clamping for turn  
off of inductive loads  
SOURCE  
Fig.1. Elements of the TOPFET.  
PINNING - SOT223  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
4
D
S
TOPFET  
input  
drain  
2
I
P
3
source  
4
drain (tab)  
2
3
1
March 1997  
1
Rev 1.200  

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