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BD7851FP-E2 PDF预览

BD7851FP-E2

更新时间: 2024-01-24 09:27:33
品牌 Logo 应用领域
罗姆 - ROHM 外围驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
25页 451K
描述
Serial / Parallel 4-input Drivers

BD7851FP-E2 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:HSSOP, SOP32,.3,32针数:25
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.84
Is Samacsys:N显示模式:SEGMENT
接口集成电路类型:SIPO BASED PERIPHERAL DRIVERJESD-30 代码:R-PDSO-G25
JESD-609代码:e2长度:13.6 mm
功能数量:1区段数:16
端子数量:25最高工作温度:85 °C
最低工作温度:-30 °C标称输出峰值电流:0.05 A
封装主体材料:PLASTIC/EPOXY封装代码:HSSOP
封装等效代码:SOP32,.3,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:2 mm子类别:Display Drivers
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
温度等级:OTHER端子面层:TIN COPPER
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:10
断开时间:0.1 µs接通时间:0.1 µs
宽度:5.4 mmBase Number Matches:1

BD7851FP-E2 数据手册

 浏览型号BD7851FP-E2的Datasheet PDF文件第4页浏览型号BD7851FP-E2的Datasheet PDF文件第5页浏览型号BD7851FP-E2的Datasheet PDF文件第6页浏览型号BD7851FP-E2的Datasheet PDF文件第8页浏览型号BD7851FP-E2的Datasheet PDF文件第9页浏览型号BD7851FP-E2的Datasheet PDF文件第10页 
Technical Note  
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS  
BU2050F】  
Pin descriptions  
Pin No.  
Pin Name  
P3  
Function  
1
2
3
4
5
6
7
8
9
P4  
Parallel Data Output  
GND  
P5  
VSS  
P6  
P7  
Parallel Data Output  
P8  
DATA  
CLK  
Serial Data Input  
Clock Signal Input  
Strobe Signal Input  
10  
11  
STB  
CLR  
In case of “L”, the data of shift register outputs.  
In case of “H”, all parallel outputs and data of latch circuit do not change.  
Reset Signal Input  
In case of “L”, the data of latch circuit reset, and all parallel output (P1P8) can be L.  
Normally CLR=H  
12  
13  
14  
P1  
P2  
Parallel Data output  
Power Supply  
VDD  
Timing chart  
CLK  
DATA8  
DATA7  
DATA6  
DATA2  
DATA1  
DATA  
CLR  
STB  
Pn  
Previous DATA  
DATA  
“L”  
Fig. 2  
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the  
DATA pin.  
2. Pn parallel output data of the shift register is set after the 8th clock by the STB.  
3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.  
Function explanation]  
A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch  
circuit is reset non-synchronously without the other input condition, and all parallel output can be “L”.  
A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock.  
In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and  
outputs from the parallel data output terminal (P1P8).  
In case of STB is “H”, all parallel outputs and the data of latch do not change.  
www.rohm.com  
© 2009 ROHM Co., Ltd. All rights reserved.  
2009.06 - Rev.A  
7/24  

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