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BD7851FP-E2 PDF预览

BD7851FP-E2

更新时间: 2024-02-07 04:04:57
品牌 Logo 应用领域
罗姆 - ROHM 外围驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
25页 451K
描述
Serial / Parallel 4-input Drivers

BD7851FP-E2 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:HSSOP, SOP32,.3,32针数:25
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.84
Is Samacsys:N显示模式:SEGMENT
接口集成电路类型:SIPO BASED PERIPHERAL DRIVERJESD-30 代码:R-PDSO-G25
JESD-609代码:e2长度:13.6 mm
功能数量:1区段数:16
端子数量:25最高工作温度:85 °C
最低工作温度:-30 °C标称输出峰值电流:0.05 A
封装主体材料:PLASTIC/EPOXY封装代码:HSSOP
封装等效代码:SOP32,.3,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:2 mm子类别:Display Drivers
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
温度等级:OTHER端子面层:TIN COPPER
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:10
断开时间:0.1 µs接通时间:0.1 µs
宽度:5.4 mmBase Number Matches:1

BD7851FP-E2 数据手册

 浏览型号BD7851FP-E2的Datasheet PDF文件第6页浏览型号BD7851FP-E2的Datasheet PDF文件第7页浏览型号BD7851FP-E2的Datasheet PDF文件第8页浏览型号BD7851FP-E2的Datasheet PDF文件第10页浏览型号BD7851FP-E2的Datasheet PDF文件第11页浏览型号BD7851FP-E2的Datasheet PDF文件第12页 
Technical Note  
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS  
BU2092F/BU2092FV】  
Pin descriptions  
Pin No.  
Pin Name  
I/O  
Function  
1
2
3
4
VSS  
DATA  
CLOCK  
LCK  
-
I
I
I
GND  
Serial Data Input  
Shift clock of DATA (Rising Edge Trigger)  
Latch clock of DATA (Rising Edge Trigger)  
Parallel Data Output (Nch Open Drain FET)  
511,  
Latch Data  
Output FET  
L
H
Q0Q11  
O
1418  
ON  
OFF  
12, 13  
17  
N.C.  
OE  
-
I
Non connected  
Output Enable (“H” level : output FET is OFF)  
Power Supply  
18  
VDD  
-
Timing chart  
CLOCK  
DATA11  
DATA10  
DATA9  
DATA1  
DATA0  
DATA  
LCK  
OE  
Qx  
“H”  
Previous DATA  
DATA110  
Note) Diagram shows a status where a pull-up resistor is connected to output.  
Fig. 4  
1. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into  
the DATA terminal.  
2. Qx parallel output data of the shift register is set after the 12th clock by the LCK.  
3. Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.  
4. Data retained in the internal latch circuit is output when the OE is in the “L” section.  
Truth Table]  
Input  
Function  
CLOCK  
DATA  
LCK  
×
OE  
H
×
×
×
×
Output (Q0Q11) Disable  
×
L
Output (Q0Q11) Enable  
Store “L” in the first stage data of shift register, the previous stage data in the  
others. (The conditions of storage register and output have no change.)  
Store “H” in the first stage data of shift register, the previous stage data in the  
others. (The conditions of storage register and output have no change.)  
The data of shift register has no change.  
L
×
×
×
H
×
×
×
×
×
×
×
×
×
×
The data of shift register is transferred to the storage register.  
The data of storage register has no change.  
www.rohm.com  
2009.06 - Rev.A  
9/24  
© 2009 ROHM Co., Ltd. All rights reserved.  

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