Datasheet > BD78320EFJ-ME2

BD78320EFJ-ME2

更新时间： 2022-12-01 22:22:37

品牌	Logo	应用领域
罗姆 - ROHM		/
页数	文件大小	规格书
28页	1636K
描述
Audio Amplifier,

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数据手册

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BD78320EFJ-ME2 数据手册

BD783xxEFJ-M Series (Including products under development)

Timing Chart – continued

(2) Start up voltage of the VDD pin and the SDB pin simultaneously

Start up the VDD pin and the SDB pin voltage simultaneously from 0.8 V or less to 4.0 V or more.

VDD,SDB

4.0 V

0.8 V

t₀

t₁

200 μs≤t₁-t₀≤1 s

t₁-t₀

t₂-t₀

BIAS

200 µs

200 ms 600 ms (Max)

1 s 1.35 s (Max)

540 ms (Max)

Turn On Time t₂-t₀depends on time period t₁-t₀in which

the VDD pin and the SDB pin voltage are started up.

VDD/2

VDD/2 × 90 %

t₂

(Turn On Time）= t₂-t₀

C₁= 0.47 μF

INP

t₃-t₂≥0 s

Start input signal

VDD/2

t₃

OUTP

VDD/2

When the VDD pin and the SDB pin voltage are started up simultaneously,

Under Voltage Lock Out is released at VDD = 3.95 V (Max) and outputs are started up.

OUTN

VDD/2

BTL

(OUTP-

OUTN)

Caution:

Start up waveforms in the figure above, are described in case the VDD pin and the SDB pin voltage are started up

from 0 V to 5 V in time period of 300 ms as an example.

Figure 16. Power On Sequence

1400

1200

1000

800

600

400

200

200 400 600 800 1000

t₁- t₀[ms]

Figure 17. Turn On Time t₂– t₀(Max) vs t₁- t₀

Caution:

Start to input signal after waiting maximum Turn On Time after setting the VDD pin and the SDB pin voltage high.

Turn On Time depends on time period in which the VDD pin and the SDB pin voltage are started up.

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TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

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