5秒后页面跳转
AS6UA5128-70BC PDF预览

AS6UA5128-70BC

更新时间: 2024-10-28 19:36:19
品牌 Logo 应用领域
ALSC 静态存储器内存集成电路
页数 文件大小 规格书
9页 118K
描述
Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, CSP, FBGA-48/36

AS6UA5128-70BC 数据手册

 浏览型号AS6UA5128-70BC的Datasheet PDF文件第3页浏览型号AS6UA5128-70BC的Datasheet PDF文件第4页浏览型号AS6UA5128-70BC的Datasheet PDF文件第5页浏览型号AS6UA5128-70BC的Datasheet PDF文件第7页浏览型号AS6UA5128-70BC的Datasheet PDF文件第8页浏览型号AS6UA5128-70BC的Datasheet PDF文件第9页 
AS6UA5128  
®
Data retention characteristics (over the operating range)13,5  
Parameter  
Symbol  
Test conditions  
Min  
1.5V  
Max  
Unit  
V
VCC for data retention  
VDR  
-
VCC = 1.5V  
CS VCC – 0.1V or  
VIN VCC – 0.1V or  
VIN 0.1V  
Data retention current  
ICCDR  
tCDR  
tR  
8
µA  
ns  
Chip deselect to data retention time  
Operation recovery time  
0
tRC  
ns  
Data retention waveform  
Data retention mode  
V
V
V
CC  
V
1.5V  
CC  
CC  
DR  
t
t
R
CDR  
V
DR  
V
V
IH  
CS  
IH  
AC test loads and waveforms  
Thevenin equivalent:  
R1  
R1  
V
R
CC  
V
TH  
CC  
V
OUTPUT  
OUTPUT  
TH  
OUTPUT  
30 pF  
5 pF  
ALL INPUT PULSES  
V
Typ  
R2  
CC  
R2  
90%  
10%  
90%  
10%  
INCLUDING  
JIG AND  
INCLUDING  
JIG AND  
SCOPE  
< 5 ns  
GND  
(a)  
SCOPE  
(b)  
(c)  
Unit  
Parameters  
R1  
V
CC = 2.7V  
1095  
VCC = 2.3V  
3800  
Ohms  
Ohms  
Ohms  
Volts  
R2  
1600  
4000  
RTH  
555  
1600  
VTH  
1.6V  
1.2V  
Notes  
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS is required to meet I specification.  
CC CC SB  
This parameter is sampled, but not 100% tested.  
For test conditions, see AC Test Conditions.  
t
and t  
are specified with CL = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage.  
CHZ  
CLZ  
This parameter is guaranteed, but not tested.  
WE is HIGH for read cycle.  
CS and OE are LOW for read cycle.  
Address valid prior to or coincident with CS transition LOW.  
All read cycle timings are referenced from the last valid address to the first transitioning address.  
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.  
11 All write cycle timings are referenced from the last valid address to the first transitioning address.  
12 N/A.  
13 1.5V data retention applies to commercial and industrial temperature range operations.  
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.  
5/25/01; v.1.1  
Alliance Semiconductor  
P. 6 of 9  

与AS6UA5128-70BC相关器件

型号 品牌 获取价格 描述 数据表
AS6UA5128-70BI ALSC

获取价格

Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, CSP, FBGA-48/36
AS6UA5128-70HFC ALSC

获取价格

SRAM
AS6UA5128-70HRC ALSC

获取价格

SRAM
AS6UA5128-70HRI ALSC

获取价格

SRAM
AS6UA5128-70STC ALSC

获取价格

SRAM
AS6UA5128-70STI ALSC

获取价格

SRAM
AS6UA5128-70TC ALSC

获取价格

SRAM
AS6UA5128-70TI ALSC

获取价格

SRAM
AS6UA5128-BC SEMICOA

获取价格

2.3V to 3.6V 512K】8 Intelliwatt low-power CMO
AS6UA5128-BI SEMICOA

获取价格

2.3V to 3.6V 512K】8 Intelliwatt low-power CMO