Datasheet > AS6UB51216-55TI

AS6UB51216-55TI

更新时间： 2024-01-26 14:14:49

品牌	Logo	应用领域
ALSC		静态存储器光电二极管
页数	文件大小	规格书
11页	184K
描述
Standard SRAM, 512KX16, 55ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

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AS6UB51216-55TI 数据手册

November 2001

Advance information

AS6UB51216

2.7V to 3.3V 512K X 16 Intelliwatt TM Super Low-Power CMOS SRAM

Features

• AS6UB51216

• 1.5V data retention

• Equal access and cycle times

• Intelliwatt™ active power circuitry

• Industrial and commercial temperature ranges available

• Organization: 524,288 words × 16 bits

• 2.7V to 3.3V power supply range

• Fast access time of 55 ns

• Easy memory expansion with CS1, CS2^*, OE inputs

• Smallest footprint packages

- 48-ball FBGA; 7.0 x 9.0 mm

- 400-mil 44-pin TSOP 2

• Low power consumption: ACTIVE

- 132 mW max at 3.3V and 55 ns

• Low power consumption: STANDBY

- 66 µW max at 3.3V

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

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Pin arrangement (top view)

Logic block diagram

44-pin 400-mil TSOP 2

512K × 16

Array

(8,388,608)

CS1

I/O1

I/O2

I/O3

I/O4

I/O16

I/O15

I/O14

I/O13

I/O1–I/O8

I/O9–I/O16

I/O

buffer

Control circuit

I/O5

I/O6

I/O7

I/O8

I/O12

I/O11

I/O10

I/O9

Column decoder

A18

A17

A16

A15

A14

A10

A9~A18

A11

A12

A13

48-CSP Ball-Grid-Array Package

CS1

CS2

I/O1

*CS2 applicable for FBGA only

I/O9 UB

I/O10 I/O11 A5

V_SSI/O12 A17

V_CCI/O13 V_SS

A6 I/O2 I/O3

A7 I/O4 V_CC

A16 I/O5 V_SS

I/O15 I/O14 A14 A15 I/O6 I/O7

I/O16 NC A12 A13 WE I/O8

A18 A8 A9

A10 A11 DNU¹

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ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢈꢉꢊꢅꢋꢁ

V_CCRange

Power Dissipation

Operating (I_CC1Standby (I_SB2

Max (mA)

)

Min

Ty p ²

(V)

Max

Speed

(ns)

Product

(V)

2.7

(V)

3.3

Max (µA)

AS6UB51216-55

AS6UB51216-70

3.0

10/30/01; V.0.9.2

Alliance Semiconductor

P. 1 of 11

12 3 4 5 6 7...11

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