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AS6UB51216-55BC PDF预览

AS6UB51216-55BC

更新时间: 2024-02-02 09:30:06
品牌 Logo 应用领域
ALSC 静态存储器内存集成电路
页数 文件大小 规格书
11页 184K
描述
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 7 X 9 MM, CSP, FBGA-48

AS6UB51216-55BC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA,
针数:48Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:55 ns
JESD-30 代码:R-PBGA-B48长度:9 mm
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:1
功能数量:1端子数量:48
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX16
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

AS6UB51216-55BC 数据手册

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November 2001  
Advance information  
AS6UB51216  
&
2.7V to 3.3V 512K X 16 Intelliwatt TM Super Low-Power CMOS SRAM  
Features  
• AS6UB51216  
• 1.5V data retention  
• Equal access and cycle times  
• Intelliwatt™ active power circuitry  
• Industrial and commercial temperature ranges available  
• Organization: 524,288 words × 16 bits  
• 2.7V to 3.3V power supply range  
• Fast access time of 55 ns  
• Easy memory expansion with CS1, CS2*, OE inputs  
• Smallest footprint packages  
- 48-ball FBGA; 7.0 x 9.0 mm  
- 400-mil 44-pin TSOP 2  
• Low power consumption: ACTIVE  
- 132 mW max at 3.3V and 55 ns  
• Low power consumption: STANDBY  
- 66 µW max at 3.3V  
• ESD protection 2000 volts  
• Latch-up current 200 mA  
ꢀꢁꢂꢃꢄꢁꢅꢆꢆꢇꢈꢉꢅꢊꢇꢋꢁꢌꢍꢎꢁꢏꢐꢑꢒꢁꢍꢓꢇꢔ  
Pin arrangement (top view)  
Logic block diagram  
44-pin 400-mil TSOP 2  
A4  
A3  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A5  
V
V
DD  
2
A6  
A2  
3
A7  
512K × 16  
Array  
(8,388,608)  
SS  
A1  
4
OE  
A0  
5
UB  
CS1  
I/O1  
I/O2  
I/O3  
I/O4  
6
LB  
I/O16  
I/O15  
I/O14  
I/O13  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
V
V
CC  
CC  
SS  
I/O1–I/O8  
I/O9–I/O16  
I/O  
buffer  
V
V
SS  
Control circuit  
I/O5  
I/O6  
I/O7  
I/O8  
WE  
I/O12  
I/O11  
I/O10  
I/O9  
A8  
Column decoder  
WE  
A18  
A17  
A16  
A15  
A14  
A9  
A10  
A9~A18  
A11  
A12  
UB  
OE  
A13  
48-CSP Ball-Grid-Array Package  
LB  
CS1  
1
2
3
4
5
6
*
CS2  
A
B
LB  
OE  
A0  
A3  
A1  
A4  
A2  
CS  
CS2  
I/O1  
*CS2 applicable for FBGA only  
I/O9 UB  
C
D
E
I/O10 I/O11 A5  
VSS I/O12 A17  
VCC I/O13 VSS  
A6 I/O2 I/O3  
A7 I/O4 VCC  
A16 I/O5 VSS  
F
I/O15 I/O14 A14 A15 I/O6 I/O7  
I/O16 NC A12 A13 WE I/O8  
A18 A8 A9  
A10 A11 DNU1  
G
H
ꢕꢁꢖꢗꢘꢁꢙꢁꢖꢍꢁꢗꢍꢚꢁꢘꢛꢋ  
ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢈꢉꢊꢅꢋꢁ  
VCC Range  
Power Dissipation  
Operating (ICC1 Standby (ISB2  
Max (mA)  
)
)
Min  
Ty p 2  
(V)  
Max  
Speed  
(ns)  
Product  
(V)  
2.7  
2.7  
(V)  
3.3  
3.3  
Max (µA)  
AS6UB51216-55  
AS6UB51216-70  
3.0  
3.0  
55  
70  
4
4
20  
20  
10/30/01; V.0.9.2  
Alliance Semiconductor  
P. 1 of 11  
Copyright © Alliance Semiconductor. All rights reserved.  

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