AS29LV800
March 2001
®
3V 1M × 8/512K × 16 CMOS Flash EEPROM
• Low power consumption
- 200 nA typical automatic sleep mode current
Features
• Organization: 1M×8/512K×16
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/BY output
• Erase suspend/resume
• Sector architecture
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
- Supports reading data from or programming data to a
sector not being erased
• Low V write lock-out below 1.5V
• Hardware RESET pin
- Resets internal state machine to read mode
CC
• 10 year data retention at 150C
• 100,000 write/erase cycle endurance
Pin arrangement
Logic block diagram
48-pin TSOP
44-pin SO
Sector protect/
erase voltage
switches
RY/BY
DQ0–DQ15
V
CC
RY/BY
A18
A17
A7
1
44
RESET
WE
V
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SS
Erase voltage
generator
Input/output
buffers
3
A8
RESET
4
A9
A6
5
A10
A11
A12
A13
A14
A15
A16
BYTE
Program/erase
control
A5
6
WE
A4
7
BYTE
A3
8
Program voltage
generator
Command
register
A2
9
AS29LV800
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
STB
Chip enable
Output enable
Logic
Data latch
CE
CE
OE
V
V
SS
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ15/A-1
DQ7
A-1
DQ14
DQ6
Y decoder
Y gating
STB
DQ13
DQ5
V
detector
Timer
CC
DQ12
DQ4
X decoder
Cell matrix
V
CC
A0–A18
Selection guide
29LV800-70R* 29LV800-80 29LV800-90 29LV800-120
Unit
ns
Maximum access time
tAA
70
70
30
80
80
30
90
90
35
120
120
50
Maximum chip enable access time
Maximum output enable access time
* Regulated voltage range of 3.0 to 3.6V
tCE
ns
tOE
ns
3/22/01; V.1.0
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