ꢀꢁꢂꢃꢁꢄꢅꢁꢆꢇꢈꢉꢉꢊ
ꢋꢀꢈꢌꢍꢎꢏꢉꢉ
&
ꢐꢎꢇꢊꢑꢇꢒꢇꢏꢓꢔꢊꢈꢕꢇꢒꢇꢊꢖꢇꢗꢑꢘꢀꢇꢙꢚꢛꢜꢝꢇ !"ꢘꢑ
ꢙꢁꢛꢃ(ꢆꢁꢜ
• Organization: 1M×8/ 512K×16
• Sector architecture
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO (availability TBD)
• Detection of program/ erase cycle completion
- DQ7 DATApolling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/ BYoutput
• Erase suspend/ resume
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/ write operations
• Sector protection
• High speed 70/ 80/ 90/ 120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/ verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/ erases chip or specified sectors
• Hardware RESET pin
- Resets internal state machine to read mode
- Supports reading data from or programming data to
a sector not being erased
• Low V write lock-out below 1.5V
CC
• 10 year data retention at 150C
• 100,000 write/ erase cycle endurance
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Sector protect/
erase voltage
switches
RY/ BY
DQ0–DQ15
V
CC
V
SS
Erase voltage
generator
Input/ output
buffers
RESET
Program/ erase
control
WE
BYTE
Program voltage
generator
Command
register
STB
Chip enable
Output enable
Logic
Data latch
CE
OE
A-1
Y decoder
Y gating
STB
VCC detector
Timer
X decoder
Cell matrix
A0–A18
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1
29LV800-70R 29LV800-80 29LV800-90 29LV800-120 Unit
Maximum access time
t
70
70
30
80
80
30
90
90
35
120
120
50
ns
ns
ns
AA
Maximum chip enable access time
Maximum output enable access time
ꢗꢉꢘꢏꢆꢓꢋꢌꢈꢏꢒꢉꢖꢁꢋꢈꢌꢆꢏꢉꢄꢌꢍꢆꢏꢉꢁꢙꢉꢚꢔꢛꢉꢈꢁꢉꢚꢔꢜꢝ
t
CE
t
OE
9/ 26/ 01; V.1.5
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