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AS29LV800T-80TI PDF预览

AS29LV800T-80TI

更新时间: 2024-11-23 22:50:11
品牌 Logo 应用领域
ANADIGICS 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 394K
描述
3V 1M】8/512K】16 CMOS Flash EEPROM

AS29LV800T-80TI 数据手册

 浏览型号AS29LV800T-80TI的Datasheet PDF文件第2页浏览型号AS29LV800T-80TI的Datasheet PDF文件第3页浏览型号AS29LV800T-80TI的Datasheet PDF文件第4页浏览型号AS29LV800T-80TI的Datasheet PDF文件第5页浏览型号AS29LV800T-80TI的Datasheet PDF文件第6页浏览型号AS29LV800T-80TI的Datasheet PDF文件第7页 
Advanced Information  
October 2000  
AS29LV800  
®
3V 1M×8/512K×16 CMOS Flash EEPROM  
• Low power consumption  
Features  
- 200 nA typical automatic sleep mode current  
• Organization: 1M×8/512K×16  
- 200 nA typical standby current  
- 10 mA typical read current  
• JEDEC standard software, packages and pinouts  
- 48-pin TSOP  
- 44-pin SO  
• Detection of program/erase cycle completion  
- DQ7 DATA polling  
- DQ6 toggle bit  
- DQ2 toggle bit  
- RY/BY output  
• Erase suspend/resume  
• Sector architecture  
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors  
- One 8K; two 4K; one 16K; and fifteen 32K word sectors  
- Boot code sector architecture—T (top) or B (bottom)  
- Erase any combination of sectors or full chip  
• Single 2.7-3.6V power supply for read/write operations  
• Sector protection  
• High speed 80/90/120 ns address access time  
• Automated on-chip programming algorithm  
- Automatically programs/verifies data at specified ad-  
dress  
- Supports reading data from or programming data to a  
sector not being erased  
• Automated on-chip erase algorithm  
- Automatically preprograms/erases chip or specified  
sectors  
• Hardware RESET pin  
- Resets internal state machine to read mode  
• Low V write lock-out below 1.5V  
CC  
• 10 year data retention at 150C  
• 100,000 write/erase cycle endurance  
Logic block diagram  
Pin arrangement  
48-pin TSOP  
44-pin SO  
Sector protect/  
erase voltage  
switches  
RY/BY  
DQ0–DQ15  
V
CC  
RY/BY  
A18  
A17  
A7  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
RESET  
WE  
V
SS  
2
Erase voltage  
generator  
Input/output  
buffers  
3
A8  
RESET  
4
A9  
A6  
5
A10  
Program/erase  
control  
A5  
6
A11  
WE  
A4  
7
A12  
BYTE  
A3  
8
A13  
Program voltage  
generator  
Command  
register  
A2  
9
A14  
A1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A15  
AS29LV800  
A0  
A16  
STB  
Chip enable  
Output enable  
Data latch  
CE  
BYTE  
VSS  
CE  
OE  
A-1  
VSS  
OE  
Logic  
DQ15/A-1  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
VCC  
DQ0  
DQ8  
DQ1  
DQ9  
DQ2  
DQ10  
DQ3  
DQ11  
Y decoder  
Y gating  
STB  
V
detector  
Timer  
CC  
X decoder  
Cell matrix  
A0–A18  
Selection guide  
29LV800-80 29LV800-90 29LV800-120  
Unit  
Maximum access time  
t
80  
80  
30  
90  
90  
35  
120  
120  
50  
ns  
ns  
ns  
AA  
Maximum chip enable access time  
Maximum output enable access time  
t
t
CE  
OE  
DID 11-40002-A. 10/19/00  
ALLIANCE SEMICONDUCTOR  
1
Copyright ©1998 Alliance Semiconductor. All rights reserved.  

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