Datasheet > ADF4355

ADF4355

更新时间： 2024-01-13 19:39:29

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	848K
描述
Microwave Wideband Synthesizer with Integrated VCO

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技术参数
数据手册

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ADF4355 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN,
针数：	32	Reach Compliance Code：	compliant
风险等级：	5.65	模拟集成电路 - 其他类型：	PHASE LOCKED LOOP
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：	0.8 mm	最大供电电压 (Vsup)：	3.45 V
最小供电电压 (Vsup)：	3.15 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	5 mm	Base Number Matches：	1

ADF4355 数据手册

Data Sheet

ADF4355

By combining the following two equations:

OPTIMIZING JITTER

ALC Wait > (50 µs × f_PFD)/Timeout

For lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of in-band noise from

the PLL. Set the PLL filter bandwidth such that the in-band noise

of the PLL intersects with the open-loop noise of the VCO,

minimizing the contribution of both to the overall noise.

Synthesizer Lock Timeout > (20 µs × f_PFD)/Timeout

The following is found:

ALC Wait = 2.5 × Synthesizer Lock Timeout

Maximize ALC Wait (to reduce Timeout to minimize time) so

that ALC Wait = 30 and Synthesizer Lock Timeout = 12.

Use the ADIsimPLL™ design tool for this task.

SPUR MECHANISMS

Finally, ALC Wait > (50 µs × f_PFD)/Timeout, is rearranged as

Timeout = Ceiling((f_PFD× 50 µs)/ALC Wait)

Timeout = Ceiling((61.44 MHz × 50 µs)/30) = 103

Synthesizer Lock Timeout

This section describes the two different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4355.

Integer Boundary Spurs

One mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (the purpose of a

fractional-N synthesizer), spur sidebands appear on the VCO

output spectrum at an offset frequency that corresponds to the

beat note or the difference in frequency between an integer

multiple of the reference and the VCO frequency. These spurs

are attenuated by the loop filter and are more noticeable on

channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth (thus

the name, integer boundary spurs).

The synthesizer lock timeout ensures that the VCO calibration

DAC, which forces V_TUNE, has settled to a steady value for the

band select circuitry.

The timeout and synthesizer lock timeout variables programmed

in Register 9 select the length of time the DAC is allowed to

settle to the final voltage before the VCO calibration process

continues to the next phase, which is VCO band selection. The

PFD frequency is used as the clock for this logic, and the

duration is set by

Timeout ×Synthesizer Lock Timeout

PFD Frequency

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop may cause a problem. Feedthrough of

low levels of on-chip reference switching noise, through the

prescaler back to the VCO, can result in reference spur levels

as high as −80 dBc.

The calculated time must be equal to or greater than 20 µs.

VCO Band Selection

Use the PFD frequency again as the clock for the band selection

process. Calculate this value by

PFD/(VCO Band Selection × 16) < 150 kHz

The band selection takes 11 cycles of the previously calculated

value. Calculate the duration by

LOCK TIME

11 × (VCO Band Selection × 16)/PFD Frequency

The PLL lock time divides into a number of settings. All of

these are modeled in the ADIsimPLL design tool. Faster lock

times than those detailed in this data sheet are possible; contact

your local Analog Devices, Inc., sales representative for more

information.

Automatic Level Calibration Timeout

Use the automatic level calibration (ALC) function to choose

the correct bias current in the ADF4355 VCO core. Calculate

the time taken by

Lock Time—A Worked Example

5 × 11 × ALC Wait × Timeout/PFD Frequency

Assuming f_PFD= 61.44 MHz,

PLL Low-Pass Filter Settling Time

VCO Band Div = Ceiling(f_PFD/2,400,000) = 26

where Ceiling() rounds up to the nearest integer.

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth. The settling time is also modeled

in the ADIsimPLL design tool.

The total lock time for changing frequencies is the sum of the

four separate times (synthesizer lock, VCO band selection, ALC

timeout, and PLL settling time) and is all modeled in the

ADIsimPLL design tool.

Rev. B | Page 31 of 35

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与ADF4355相关器件

型号	品牌	获取价格	描述	数据表
ADF4355_17	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-2	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-2_17	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-2BCPZ	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-2BCPZ-RL7	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-3	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-3_17	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-3BCPZ	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355-3BCPZ-RL7	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO
ADF4355BCPZ	ADI	获取价格	Microwave Wideband Synthesizer with Integrated VCO

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