Datasheet > ADF4355

ADF4355

更新时间： 2024-02-27 16:50:22

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	848K
描述
Microwave Wideband Synthesizer with Integrated VCO

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技术参数
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ADF4355 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN,
针数：	32	Reach Compliance Code：	compliant
风险等级：	5.65	模拟集成电路 - 其他类型：	PHASE LOCKED LOOP
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：	0.8 mm	最大供电电压 (Vsup)：	3.45 V
最小供电电压 (Vsup)：	3.15 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	5 mm	Base Number Matches：	1

ADF4355 数据手册

ADF4355

Data Sheet

7. Wait >16 ADC_CLK_DIV cycles. For example, if

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 43).

ADC_CLK_DIV = 99.417 kHz, wait 16/99417 sec =

161 µs. See the Register 10 section.

8. Register 0 (autocalibration enabled [DB21 = 1]).

In this example, divide the 122.88 MHz reference signal by 2 to

generate a f_PFDof 61.44 MHz. The desired channel spacing is

200 kHz.

For f_PFD> 75 MHz (initially lock with half f_PFD), use the

following sequence:

f_PFD

OUT

PFD

VCO

÷2

1. Register 10.

2. Register 4 (counter reset enabled [DB4 = 1]).

3. Register 2 (for halved f_PFD).

DIVIDER

4. Register 1 (for halved f_PFD).

Figure 43. Loop Closed Before Output Divider

5. Register 0 (for halved f_PFD; autocalibration disabled).

6. Register 4 (counter reset disabled [DB4 = 0], with the

R divider doubled to output half f_PFD).

7. Wait >16 ADC_CLK cycles. For example, if

ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.

See the Register 10 section for more information.

8. Register 0 (for halved f_PFD; autocalibration enabled).

9. Register 4 (with the R divider set for desired f_PFD).

10. Register 2 (for desired f_PFD).

The worked example is as follows:

•

N = VCO_OUT/f_PFD= 4225.6 MHz/61.44 MHz =

68.7760416666666667

INT = int(VCO frequency/f_PFD) = 68

FRAC = 0.7760416666666667

•

MOD1 = 16,777,216

FRAC1 = int(MOD1 × FRAC) = 13019817

Remainder = 0.6666666667 or 2/3

MOD2 = f_PFD/GCD(f_PFD/f_CHSP) = 61.44

MHz/GCD(61.44 MHz/200 kHz) = 1536

FRAC2 = remainder × 1536 = 1024

11. Register 1 (for desired f_PFD).

12. Register 0 (for desired f_PFD; autocalibration disabled).

The frequency change only occurs when writing to Register 0.

•

RF SYNTHESIZER—A WORKED EXAMPLE

From Equation 8,

Use the following equations to program the ADF4355 synthesizer:

f_PFD= (122.88 MHz × (1 + 0)/2) = 61.44 MHz

(9)

FRAC2

MOD2

MOD1

From Equation 7,

FRAC1+

RF_OUT

where:

INT +

× (f_PFD)/RF Divider (7)

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/2²⁴))/2

where:

INT = 68

FRAC1 = 13,019,817

FRAC2 = 1024

(10)

RF_OUTis the RF frequency output.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality.

MOD2 is the auxiliary modulus.

MOD1 is the fixed 24-bit modulus.

MOD2 = 1536

RF Divider = 2 (see Equation 7)

RF Divider is the output divider that divides down the VCO

frequency.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system, increase the PFD frequency. Doubling the PFD

frequency usually improves noise performance by 3 dB.

_PFD= REF_IN× ((1 + D)/(R × (1 + T)))

(8)

where:

REF_INis the reference frequency input.

D is the RF REF_INdoubler bit.

R is the RF reference division factor.

T is the reference divide by 2 bit (0 or 1).

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

For example, in a universal mobile telecommunication system

(UMTS) where 2112.8 MHz RF frequency output (RF_OUT) is

required, a 122.88 MHz reference frequency input (REF_IN) is

available. Note that the ADF4355 VCO operates in the frequency

range of 3.4 GHz to 6.8 GHz. Therefore, an RF divider of 2 must

be used (VCO frequency = 4225.6 MHz, RF_OUT= VCO frequency/

RF divider = 4225.6 MHz/2 = 2112.8 MHz).

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these bandwidths usually have a long lock time. A wider

loop bandwidth achieves faster lock times but may lead to

increased spurious signals inside the loop bandwidth.

Rev. B | Page 30 of 35

1...27 28 293031 32 33...35

中文翻译

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