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ADF4355

更新时间： 2024-02-16 22:55:32
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
35页 848K
描述
Microwave Wideband Synthesizer with Integrated VCO

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ADF4355 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：32Reach Compliance Code：compliant
风险等级：5.65模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm湿度敏感等级：3
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：0.8 mm最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：5 mmBase Number Matches：1

ADF4355 数据手册

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Data Sheet  
ADF4355  
The bottom of the chip-scale package has a central exposed  
POWER SUPPLIES  
thermal pad. The thermal pad on the PCB must be at least as  
large as the exposed pad. On the PCB, there must be a minimum  
clearance of 0.25 mm between the thermal pad and the inner  
edges of the pad pattern. This clearance ensures the avoidance  
of shorting.  
The ADF4355-2 contains four multiband VCOs that cover an  
octave range of frequencies. To ensure best performance, it is vital  
to connect a low noise regulator, such as the ADM7170, to the  
VVCO pin. Connect the same regulator to package pins VVCO  
,
VREGVCO, and VP.  
To improve the thermal performance of the package, use thermal  
vias on the PCB thermal pad. If vias are used, incorporate them  
into the thermal pad at the 1.2 mm pitch grid. The via diameter  
must be between 0.3 mm and 0.33 mm and the via barrel must  
be plated with 1 oz. of copper to plug the via.  
For the 3.3 V supply pins, use two ADM7170 regulators, one for  
the DVDD and AVDD supplies and one for VRF. Figure 45 shows  
the recommended connections.  
PRINTED CIRCUIT BOARD (PCB) DESIGN  
GUIDELINES FOR A CHIP-SCALE PACKAGE  
For a microwave PLL and VCO synthesizer, such as the ADF4355,  
take care with the board stack-up and layout. Do not consider  
using FR4 material because it is too lossy above 3 GHz. Instead,  
Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is  
suitable.  
The lands on the 32-lead lead frame chip-scale package are  
rectangular. The PCB pad for these lands must be 0.1 mm  
longer than the package land length and 0.05 mm wider than  
the package land width. Center each land on the pad to  
maximize the solder joint size.  
Take care with the RF output traces to minimize discontinuities  
and ensure the best signal integrity. Via placement and grounding  
are critical.  
V
= 3.3V  
OUT  
V
= 6.0V  
IN  
VIN  
EN  
VOUT  
VOUT  
C
10µF  
IN  
C
10µF  
OUT  
ON  
SENSE  
OFF  
ADM7170  
SS  
C
SS  
1nF  
LOCK  
GND  
DETECT  
100nF  
100nF  
1
17  
V
25  
26  
C
CE PDB V  
RF RF  
10  
6
27  
DV  
16  
AV  
4
32  
30  
2
C
REG  
V
MUXOUT  
REG  
VCO  
P
DD  
DD  
1nF 1nF  
1nF 1nF  
V
= 3.3V  
C
OUT  
FREF  
FREF  
29  
IN  
REF  
A
B
IN  
IN  
V
= 6.0V  
RF  
B+ 14  
IN  
OUT  
VIN  
EN  
VOUT  
VOUT  
V
OUT  
C
RF  
B–  
IN  
15  
28 REF  
OUT  
IN  
OUT  
10µF  
ON  
10µF  
7.5nH  
7.5nH  
SENSE  
1
2
3
CLK  
OFF  
1nF  
1nF  
ADM7170  
DATA  
LE  
11  
12  
RF  
RF  
A+  
A–  
SS  
OUT  
C
ADF4355  
SS  
1nF  
OUT  
GND  
V
20  
7
TUNE  
3.3kΩ  
22  
R
CP  
OUT  
SET  
4.7kΩ  
33nF  
V
= 5.0V  
C
V
= 6.0V  
OUT  
IN  
1500pF  
390pF  
AV  
5
DD  
VIN  
EN  
VOUT  
VOUT  
1kΩ  
C
CP  
SD  
A
A
A
V
V
V
BIAS  
IN  
GND  
GND GND  
GNDRF  
GNDVCO  
REGVCO  
REF  
OUT  
10µF  
ON  
10µF  
8
31  
9
13  
18 21  
19  
23  
24  
SENSE  
OFF  
ADM7170  
SS  
C
SS  
1nF  
10pF  
0.1µF 10pF  
0.1µF 10pF  
0.1µF  
GND  
Figure 45. ADF4355 Power Supplies  
Rev. B | Page 33 of 35  
 
 
 
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