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ADF4355

更新时间： 2024-01-21 06:35:15
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
35页 848K
描述
Microwave Wideband Synthesizer with Integrated VCO

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ADF4355 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：32Reach Compliance Code：compliant
风险等级：5.65模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm湿度敏感等级：3
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：0.8 mm最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：5 mmBase Number Matches：1

ADF4355 数据手册

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Data Sheet  
ADF4355  
CONTROL  
BITS  
RESERVED  
RESYNC CLOCK  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
P13 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1  
P12  
C1(0)  
C3(1) C2(0)  
0
0
0
0
0
1
0
0
0
0
0
1
P16  
P15  
C4(1)  
P14  
P16  
P15  
...  
P5  
P4  
P3  
P2  
P1  
RESYNC CLOCK  
0
0
0
.
0
0
0
.
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
NOT ALLOWED  
1
2
...  
0
0
0
.
0
0
0
.
1
1
1
.
0
0
1
.
1
1
0
.
1
1
0
.
0
1
0
.
22  
23  
24  
...  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65533  
65534  
65535  
Figure 42. Register 12  
For fPFD > 75 MHz (initially lock with half fPFD), use the  
following sequence:  
1. Register 12.  
REGISTER 12  
Control Bits  
With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 42  
shows the input data format for programming this register.  
2. Register 11.  
3. Register 10.  
4. Register 9.  
Phase Resync Clock Divider Value  
5. Register 8.  
6. Register 7.  
7. Register 6.  
8. Register 5.  
P16 to P1 (Bits[DB31:DB16]) set the timeout counter for  
activation of phase resync. This value must be set such that a  
resync happens immediately after (and not before) the PLL has  
achieved lock after reprogramming.  
9. Register 4 (with the R divider doubled to output half fPFD).  
10. Register 3.  
11. Register 2 (for halved fPFD).  
Calculate the timeout value using the following equation:  
Time Out Value = Phase Resync Clock/PFD Frequency  
Reserved  
12. Register 1 (for halved fPFD).  
13. Wait >16 ADC_CLK cycles. For example, if  
ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.  
See the Register 10 section for more information.  
14. Register 0 (for halved fPFD; autocalibration enabled).  
15. Register 4 (with the R divider set for desired fPFD).  
16. Register 2 (for desired fPFD).  
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set  
to 1, but all other bits in this range must be set to 0.  
REGISTER INITIALIZATION SEQUENCE  
At initial power-up, after the correct application of voltages to  
the supply pins, registers must be programmed in sequence. For  
17. Register 1 (for desired fPFD).  
18. Register 0 (for desired fPFD; autocalibration disabled).  
f
PFD ≤ 75 MHz, use the following sequence:  
1. Register 12.  
2. Register 11.  
3. Register 10.  
4. Register 9.  
5. Register 8.  
6. Register 7.  
7. Register 6.  
8. Register 5.  
9. Register 4.  
10. Register 3.  
11. Register 2.  
12. Register 1.  
13. Wait >16 ADC_CLK cycles. For example, if  
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs.  
See the Register 10 section for more information.  
14. Register 0.  
FREQUENCY UPDATE SEQUENCE  
Frequency updates require updating the auxiliary modulator  
(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,  
and the integer value (INT) in Register 0. It is recommended to  
perform a temperature dependent VTUNE calibration by updating  
Register 10 first. A counter reset (Bit DB4) is also required in  
the frequency update sequence Therefore, for fPFD ≤ 75 MHz,  
use the following sequence:  
1. Register 10.  
2. Register 4 (counter reset enabled [DB4 = 1]).  
3. Register 2.  
4. Register 1.  
5. Register 0 (autocalibration disabled [DB21 = 0]).  
6. Register 4 (counter reset disabled [DB4 = 0]).  
Rev. B | Page 29 of 35  
 
 
 
 
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