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ADCLK854 PDF预览

ADCLK854

更新时间: 2024-02-28 05:16:24
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
16页 532K
描述
1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer

ADCLK854 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:unknown风险等级:5.75
Is Samacsys:N放大器类型:BUFFER
最大平均偏置电流 (IIB):350 µAJESD-30 代码:S-XQCC-N48
JESD-609代码:e3长度:7 mm
湿度敏感等级:NOT APPLICABLE功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1 mm
子类别:Buffer Amplifier供电电压上限:2 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mmBase Number Matches:1

ADCLK854 数据手册

 浏览型号ADCLK854的Datasheet PDF文件第7页浏览型号ADCLK854的Datasheet PDF文件第8页浏览型号ADCLK854的Datasheet PDF文件第9页浏览型号ADCLK854的Datasheet PDF文件第11页浏览型号ADCLK854的Datasheet PDF文件第12页浏览型号ADCLK854的Datasheet PDF文件第13页 
ADCLK854  
900  
800  
700  
600  
500  
400  
–80  
–90  
ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT  
E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A  
WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672),  
WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A  
WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D).  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
–180  
ADCLK854  
CLOCK SOURCE  
10  
100  
1k  
10k  
100k  
1M  
10M  
100M  
FREQUENCY OFFSET (Hz)  
INPUT FREQUENCY (MHz)  
Figure 9. LVDS Differential Output Swing vs. Input Frequency  
Figure 12. Absolute Phase Noise LVDS @ 1000 MHz  
350  
300  
250  
200  
150  
100  
50  
325  
300  
275  
250  
225  
200  
175  
150  
125  
100  
75  
ALL BANKS CMOS  
2 BANKS CMOS  
1 BANK LVDS  
1 BANK CMOS  
2 BANKS LVDS  
50  
ALL BANKS LVDS  
25  
0
0
25  
0
200  
400  
600  
800 1000 1200 1400 1600 1800  
50  
75  
100  
125  
150  
175  
200  
225  
250  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 10. LVDS Current vs. Frequency; All Banks Set to LVDS  
Figure 13. LVDS/CMOS Current vs. Frequency with Various Logic  
Combinations  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
0
0
0.5  
1.0  
1.5  
2.0  
2.5  
0
50  
100  
150  
200  
250  
INPUT SLEW RATE (V/ns)  
FREQUENCY (MHz)  
Figure 11. Additive Broadband Jitter vs. Input Slew Rate  
Figure 14. CMOS Output Duty Cycle vs. Frequency (10 pF Load)  
Rev. 0 | Page 10 of 16  
 
 
 

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