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AD9548 PDF预览

AD9548

更新时间: 2024-01-12 22:17:16
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
112页 1935K
描述
Quad/Octal Input Network Clock Generator/Synchronizer

AD9548 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:88
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.64
JESD-30 代码:S-XQCC-N88JESD-609代码:e3
长度:12 mm湿度敏感等级:3
端子数量:88最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
主时钟/晶体标称频率:1000 MHz认证状态:Not Qualified
座面最大高度:0.9 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:12 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

AD9548 数据手册

 浏览型号AD9548的Datasheet PDF文件第7页浏览型号AD9548的Datasheet PDF文件第8页浏览型号AD9548的Datasheet PDF文件第9页浏览型号AD9548的Datasheet PDF文件第11页浏览型号AD9548的Datasheet PDF文件第12页浏览型号AD9548的Datasheet PDF文件第13页 
AD9548  
TIME DURATION OF DIGITAL FUNCTIONS  
Table 13.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
TIME DURATION OF DIGITAL FUNCTIONS  
EEPROM-to-Register Download Time  
25  
ms  
Using default EEPROM storage  
sequence (see Register 0E10 to  
Register 0E3F)  
Register-to-EEPROM Upload Time  
Minimum Power-Down Exit Time  
Maximum Time from Assertion of the RESET  
pin to the M0 to M7 Pins Entering High  
Impedance State  
200  
ms  
Using default EEPROM storage  
sequence (see Register 0E10 to  
Register 0E3F  
10.5  
45  
ꢀs  
ns  
Dependent on loop-filter bandwidth  
DIGITAL PLL  
Table 14.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DIGITAL PLL  
Phase-Frequency Detector (PFD)  
Input Frequency Range  
1
107  
105  
Hz  
Maximum fPFD1: fS/1002  
Loop Bandwidth  
0.001  
Hz  
Programmable design parameter; maximum  
fLOOP = fREF/(20R)3  
Phase Margin  
30  
1
8
89  
Degrees  
Programmable design parameter  
1, 2, …, 1,073,741,824  
8, 9, …, 1,073,741,824  
Reference Input (R) Division Factor  
Integer Feedback (S) Division Factor  
Fractional Feedback Divide Ratio  
230  
230  
0.999  
0
Maximum value: 1022/1023.  
1 fPFD is the frequency at the input to the phase-frequency detector.  
2 fS is the sample rate of the output DAC.  
3 fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.  
DIGITAL PLL LOCK DETECTION  
Table 15.  
Parameter  
Min  
Typ  
1
Max  
Unit  
Test Conditions/Comments  
PHASE LOCK DETECTOR  
Threshold Programming Range  
Threshold Resolution  
0.001  
65.5  
ns  
ps  
FREQUENCY LOCK DETECTOR  
Threshold Programming Range  
Threshold Resolution  
0.001  
16,700  
ns  
ps  
Reference-to-feedback period difference  
1
HOLDOVER SPECIFICATIONS  
Table 16.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
HOLDOVER SPECIFICATIONS  
Frequency Accuracy  
<0.01  
ppm  
Excludes frequency drift of SYSCLK source;  
excludes frequency drift of input reference prior  
to entering holdover  
Rev. 0 | Page 10 of 112  
 
 

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